Fabricating method of vertical transistor

Details Fabricating method of vertical transistor Fabricating method of vertical transistor

2011-08-23

2011-08-23

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S242000, C257SE21410, C257SE21629

Reexamination Certificate

active

08003457

ABSTRACT:
A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar.

REFERENCES:
patent: 2006/0038205 (2006-02-01), Abbott et al.

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