Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-03-20
2008-12-02
Doan, Theresa T (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S591000, C438S592000
Reexamination Certificate
active
07459383
ABSTRACT:
A gate structure comprising a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer is provided. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate dielectric layer and has an opening. Part of the second conductive layer is disposed in the opening. The second conductive layer has an extrusion that protrudes above the opening of the first conductive layer. The extrusion has a cross-sectional width less than the width of the second conductive layer inside the opening. The cap layer is disposed on the extrusion. The first insulating spacer is disposed on part of the first conductive layer and covers the sidewalls of the extrusion. The inclusion of the extrusion in the second conductive layer decreases the resistance of the gate structure and promotes the efficiency of the device.
REFERENCES:
patent: 5726479 (1998-03-01), Matsumoto et al.
patent: 6107171 (2000-08-01), Tsai
patent: 6544871 (2003-04-01), Honeycutt
patent: 2004/0121166 (2004-06-01), Ni et al.
Doan Theresa T
Jianq Chyun IP Office
ProMOS Technologies Inc.
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