Fabricating method of a flash memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S596000, C257SE21682

Reexamination Certificate

active

07445999

ABSTRACT:
A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

REFERENCES:
patent: 5889304 (1999-03-01), Watanabe et al.
patent: 6487117 (2002-11-01), Choi et al.
patent: 6720610 (2004-04-01), Iguchi et al.

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