Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-08-02
2008-11-04
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000, C257SE21682
Reexamination Certificate
active
07445999
ABSTRACT:
A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.
REFERENCES:
patent: 5889304 (1999-03-01), Watanabe et al.
patent: 6487117 (2002-11-01), Choi et al.
patent: 6720610 (2004-04-01), Iguchi et al.
Huang Cheng-Tung
Pittikoun Saysamone
Wang Leo
Chaudhari Chandra
Jianq Chyun IP Office
Powerchip Semiconductor Corp.
LandOfFree
Fabricating method of a flash memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabricating method of a flash memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabricating method of a flash memory cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4035457