Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-04
2001-07-24
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S770000, C438S981000
Reexamination Certificate
active
06265267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device comprising gate oxide layers of various thicknesses. More particularly, the present invention relates to a fabrication method for a flash memory cell comprising gate oxide layers of various thicknesses.
2. Description of the Related Art
To lower manufacturing cost and to simplify the manufacturing procedures for a semiconductor device, integrating different devices, such as the memory cell and the logic circuit on the same wafer has become a trend in the semiconductor industry. Examples of such are the embedded dynamic random access memory (DRAM) in which a dynamic random access memory cell and a logic circuit device are constructed on the same wafer and the embedded flash memory cell in which a flash memory cell and a logic circuit device are integrated on the same wafer.
In order for the memory cell device to be reliable, the logic circuit device to have high performance and to have different voltages applied to the device, it is necessary to manufacture gate oxide layers with various thicknesses during the fabrication of a wafer with integrated devices such as the memory cell and the logic circuit region, which is essential for accommodating the demands of the device operations.
FIGS. 1A
to
1
D are schematic, cross-sectional views showing the manufacturing of an embedded flash memory cell. As shown in
FIG. 1A
, a substrate
100
comprises a memory cell region
102
and a logic circuit region
104
, wherein between the memory cell region
102
and the logic circuit region
104
, and between devices are isolated by isolation structures
106
. The memory cell region
102
comprises a floating gate
108
, wherein insulation between the floating gate
108
and the substrate
100
is provided by a gate oxide layer
110
. An oxide
itride/oxide (ONO) layer
112
is then formed on the memory cell region
102
and the logic circuit region
104
. The ONO layer
112
formed on the floating gate
108
serves as a dielectric layer between the flash memory floating gate
108
and the control gate formed subsequently.
Thereafter, a photoresist
114
is formed on the ONO layer
112
. Using the photoresist
114
to define the ONO layer
112
, the ONO layer
112
in the logic circuit region
104
is removed, exposing the substrate
100
as illustrated in FIG.
1
B. Continuing to
FIG. 1C
, the photoresist
114
is removed. A gate oxide layer
116
is then formed on the exposed substrate
100
in the logic circuit region
104
(as in FIG. B).
Still referring to
FIG. 1C
, the same procedures are being conducted in which a photoresist
122
is used to cover the memory cell region
102
and a portion of the logic circuit region
104
. The portion of the gate oxide layer
116
not covered by the photoresist
122
is removed, exposing the substrate
100
. A gate oxide layer
116
′ of a different thickness is then formed on the exposed substrate
100
, followed by removing the photoresist
122
.
Referring to
FIG. 1D
, a control gate
118
a
is further formed on the ONO layer
112
, and gates
118
b
,
118
c
are formed on the gate oxide layers
116
,
116
′ respectively. Source/drain regions are then formed on both sides of each gate.
Although in the above manufacturing process, gate oxide layers
110
,
116
,
116
′ of various thicknesses are formed to accommodate the operating demands of the device, the photoresists
114
,
122
are in a direct contact with the ONO layer
112
during the defining processes. The gate oxide layer
116
, which also undergoes a photolithography procedure, is in direct contact with the photoresist
122
. Contamination from photoresists
114
,
122
, which are generally formed with an organic material, easily diffuse into the ONO layer
112
and the gate oxide layer
116
when the photoresists are placed in a direct contact with the ONO layer
112
or the gate oxide layer
116
. Furthermore, the removal of the photoresists
116
,
112
, for example by plasma, easily induces damages in the underlying materials. With the high demand for the reliability of the ONO layer
112
and the gate oxide layer
116
, the problems of contamination and potential damages induced by the photoresist mentioned above lower the reliability of the ONO layer and seriously affect the device operating efficiency.
SUMMARY OF THE INVENTION
Based on the foregoing, the current invention provides a fabrication method for a semiconductor device comprising various thicknesses of gate oxide layers. The method is applicable to a substrate, wherein the substrate comprises a first region and a second region. The first region further comprises a first conductive layer, isolated from the substrate by a first gate oxide layer. Thereafter, a first oxide layer
itride layer is formed on the first conductive layer. A doped polysilicon layer is then formed on the first oxide
itride layer of the first region, wherein the doped polysilicon layer is not formed in the second region. Subsequently, a second gate oxide layer is formed on the substrate of the second region. Concurrently, a first oxide layer
itride layer/second oxide layer is formed from the first oxide layer
itride layer/doped polysilicon layer. After this, a defined second conductive layer is formed on the first oxide layer
itride layer/ second oxide layer and on the second conductive layer.
The present invention further provides a fabrication method for an embedded flash memory cell, which is applicable to a substrate comprising a memory cell region, a first logic circuit region and a second logic circuit region. A floating gate is then formed on the memory cell region, wherein the floating gate is isolated from the substrate by a gate oxide layer. A first oxide layer
itride layer is then formed on the floating gate. After this, a doped polysilicon layer is formed on the memory cell, not covering but rather exposing the first logic circuit region or the second logic circuit region. Subsequently, the first doped polysilicon layer is converted to a first dioxide layer. A second gate oxide layer is also formed in the first and the second logic circuit regions, and the first oxide layer
itride layer/second oxide layer in the memory cell region forms one of the inner dielectric layer for the flash memory cell. A second doped polysilicon layer is then formed on the substrate, followed by removing the second doped polysilicon layer and the second gate oxide layer in the second logic circuit region, and thus exposing the substrate in the second logic circuit region. Thereafter, a third gate oxide layer is formed on the exposed substrate in the second logic circuit region, followed by forming a defined conductive layer on the substrate in which a control gate is formed in the memory cell region. A first gate and a second gate are also formed in the first logic circuit region and the second logic circuit region, respectively.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5104819 (1992-04-01), Friberger et al.
patent: 5665620 (1997-09-01), Nguyen et al.
patent: 6133093 (2000-10-01), Prinz et al.
patent: 6162683 (2000-12-01), Chen
patent: 6180539 (2001-01-01), Tung
Wolf et al., “Silicon Processing for the VLSI Era vol. 1: Process Technology”, pp. 213-215, Lattice Press, 1986.
Booth Richard
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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