Fabricating a die with test enable circuits between embedded...

Details Fabricating a die with test enable circuits between embedded... Fabricating a die with test enable circuits between embedded...

2006-06-06

2006-06-06

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S123000, C714S030000, C714S719000

Reexamination Certificate

active

07056752

ABSTRACT:
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

REFERENCES:
patent: 5506499 (1996-04-01), Puar
patent: 6097098 (2000-08-01), Ball
patent: 6180426 (2001-01-01), Lin
patent: 6535999 (2003-03-01), Merritt et al.

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