Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-14
2006-02-14
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S314000
Reexamination Certificate
active
06998314
ABSTRACT:
Methods and devices are disclosed which provide for memory devices having reduced memory cell square feature sizes. Such square feature sizes can permit large memory devices, on the order of a gigabyte or large, to be fabricated on one chip or die. The methods and devices disclosed, along with variations of them, utilize three dimensions as opposed to other memory devices which are fabricated in only two dimensions. Thus, the methods and devices disclosed, along with variations, contains substantially horizontal and vertical components.
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Nakagawa et al.; A Flash EEPROM Cell with Self-Aligned Trench Transistor & Isolation Structure, ULSI Device Development Laboratory, VLSI Manufacturing Engineering Division, NEC Corporation, p. 1123, Shimokuzawa, Sagamihara, Japan.
Coleman W. David
Dinsmore & Shohl LLP
LandOfFree
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