Computer graphics processing and selective visual display system – Computer graphics display memory system – Cache
Reexamination Certificate
2001-10-03
2004-08-17
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Cache
C345S531000, C345S554000, C345S556000, C345S559000, C711S122000
Reexamination Certificate
active
06778179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to graphics frame buffer architecture.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the memory systems that form an integral part of the graphics system. Attempts to further improve graphics system performance are now running up against the limitations of these memory systems in general, and memory device limitations in particular.
In order to provide memory systems with increased data handling rates and capacities, system architects may employ consistently higher levels of integration. One example of increased integration is the 3D-RAM family of memories from the Mitsubishi Corporation. The 3D-RAM incorporates four banks of DRAM main storage with level one and level two cache memories, and a bank-swapped shift register capable of providing an uninterrupted stream of sequential data at current pixel clock speeds.
Some previous incarnations of the 3D-RAM architecture have included cache management functions as well. In these older devices, circuitry was integrated to allow for the efficient write-back of modified or “dirty” data in the level one cache to the level two cache, and ultimately back to the DRAM. However, as these devices have grown in capacity and performance, it has become increasingly difficult and costly to integrate these cache management functions. In the most recent 3D-RAM device, the 3D-RAM64 these cache management functions have been abandoned altogether having finally become economically infeasible. Despite exclusion within the 3D-RAM devices, these cache management functions are still desirable as they may significantly decrease power consumption and increase memory performance. Furthermore, the cache management functions may also provide the ability to accomplish a maskable write operation from level one to level two cache memories. A maskable write operation between the two cache memories may provide an efficient means for performing area and pattern fills, both of rectangular and irregularly shaped areas. For these reasons, a system and method for externally managing the cache memory of 3D-RAM devices employed in graphics systems is desired.
SUMMARY OF THE INVENTION
The problems set forth above may at least in part be solved in some embodiments by a system or method for managing a 3D-RAM cache through the employment of external dirty tag bits. In one embodiment, the system may include a memory array of 3D-RAM devices configured to receive and store pixel data. A memory request processor may be connected to the memory and may be configured to maintain an array of dirty tag bits (i.e., setting and clearing the logic state of the dirty tag bits in response to cache requests and pixel write operations). The memory request processor may be further configured to periodically synchronize the pixel data in the 3D-RAM level two and level one caches by commanding level one cache write-backs. These write-back operations may be modified by the memory request processor to incorporate the information stored in the dirty tag bits, thus allowing only modified pixel data in the level one cache to be written-back. This may be accomplished by placing the dirty tag bit contents on the 3D-RAM DRAM control bus on the cycle subsequent to the cycle containing the write-back command.
As noted above, a method for managing 3D-RAM cache through the employment of external dirty tag bits is also contemplated. In one embodiment, the method includes grouping the dirty tag bits into status words, where each status word is associated with a block of level one cache memory. The blocks of level one cache memory are examined sequentially by first waiting for an empty memory cycle. Next, the status word associated with the block under examination is retrieved and the dirty tag bits are tested. If the test indicates that any pixel data has been modified, then a block write-back is requested. The status word is transferred along with the request in order that only the modified pixel values are written-back to the level two cache. Next, the status word is updated to indicate that all pixel data within the block under examination is unmodified.
In one embodiment, the cache management system may be integrated into a graphics system suitable for creating and displaying graphic images. In other embodiments, the system may be part of an optional assembly, communicating with a host graphics system through the use of a data or control bus specific to the host.
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Kubalska Ewa M.
Lavelle Michael G.
Tang Yan Yan
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Tung Kee M.
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