Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2002-11-05
2004-08-24
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S257000
Reexamination Certificate
active
06780785
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to flash memory cells, and, more particularly, to a method to form flash memory cells with a unique erasing gate structure.
(2) Description of the Prior Art
EEPROM or flash EEPROM memory is frequently used in electronic systems. EEPROM provides a medium for data storage that can withstand power interruption without losing data. Typical EEPROM cells comprise a form of a MOS transistor having a floating gate and a control gate. The floating gate is constructed so that it can be charged or discharged. The charge state can be maintained over an indefinite period. The control gate is used both in the program/erase operation and in the reading operation. The charge state of the floating gate determines the relative threshold voltage of the flash transistor and this, in turn, determines if a “0” or a “1” value has been stored.
Referring now to
FIG. 1
, a typical flash cell is shown. This flash cell comprises two transistors, each further comprising a floating gate
14
, a control gate
18
, a drain region
42
, and a common source region
38
. This shared source arrangement is found to be an efficient way to layout flash cells in a large array. The flash cell is constructed on a substrate
10
. The drains
42
and sources
38
are formed in the substrate
10
. The floating gates
14
typically comprise a polysilicon layer
26
overlying the substrate
10
with a gate oxide layer
22
therebetween. In this flash cell example, the control gates
18
are adjacent to the floating gates
14
in what is called a split gate arrangement. The control gates
18
comprise another polysilicon layer
28
adjacent to the floating gate polysilicon
26
with a second gate oxide layer
34
therebetween. In addition, the control gates
18
overlie the substrate
10
with the second gate oxide
34
therebetween.
In this configuration, the channel region between the drain
42
and source
38
of either flash transistor is controlled by two gates. First, the floating gate
14
couples stored charge and capacitively coupled charge from the control gate
18
onto a first part of the channel. Second, the control gate
18
couples charge onto the channel. This split gate arrangement has a particular advantage over flash transistors where the control gate is stacked over the floating gate. Namely, the control gate
18
can completely shut off the channel when the cell is not selected. This insures that no leakage current is generated by an unselected cell regardless of the charge state of the floating gate
14
. This is a particularly useful feature for cases where the floating gate
14
has been over-erased such that the threshold voltage is reduced to below zero volts.
It should be noted the control gate
18
is used for several functions in the flash cell. In particular, the control gate
18
is used for erasing the cell. In the erasing operation, a high voltage is forced onto control gate
18
, also called the word line, of the cell. For example, the word line
18
is forced to about 12 Volts while the common source
38
and drain
42
, also called the bit line drain, are forced to 0 Volts. In this operation, electrons are injected from the floating gate
14
into the control gate
18
to cause the floating gate
14
to be erased. In the programming operation, the word line
18
is forced to about 2.5 Volts while the common source
38
is forced to a high voltage of about 10 Volts and the bit line drain
42
is forced to about 0.5 Volts. This condition causes source side
38
injection of electrons from the substrate
10
to the floating gate
14
and results in programming. Finally, during a reading operation, the word line gate is forced to about 2.5 Volts while the common source
38
is forced to about 0 Volts and the bit line drain
42
is forced to about 1.5 Volts. This condition will detect the presence of channel current to verify the state of the cell (“0” or “1”).
The above-described operating conditions imply that the thickness Y of the dielectric between the control gate
18
and the substrate
10
should be large to withstand a large gate-to-substrate voltage during erasing without gate oxide breakdown. Further, the distance X between the control gate
18
and the floating gate channel should be small to increase the lateral electric field and to aid in generating hot electron injection. Finally, the thickness Z of the dielectric between the control gate
18
and the floating gate
14
should be small to provide high current gain for the flash device during reading. However, in this prior art device, a single dielectric layer
34
must meet all of these requirements. In particular, the second gate oxide layer
34
must meet be both thick enough to withstand the erasing mode and thin enough to provide efficient programming and reading. It is found that the multiple use, control gate
18
and single thickness dielectric layer
34
are not capable of meeting the performance requirements for future flash systems.
Several prior art inventions relate flash memory cells having control gates and erase gates. U.S. Pat. Nos. 6,101,131, 6,125,060, and 6,261,907 B1 to Chang disclose a flash EEPROM device having an erasing gate terminal. The erasing gate is formed beside a control gate/flash gate stack. The erasing gate overlies and controls a part of the active channel. U.S. Pat. No. 6,274,436 B1 to Kao et al describes a flash EEPROM cell having an erase gate. The floating gate is formed. A control gate is formed overlying part of the floating gate and a part of the channel in split-gate form. An erase gate is formed overlying another part of the floating gate and the channel.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable flash memory device.
A further object of the present invention is to provide a method to form a flash memory device with improved programming and erasing efficiency.
A yet further object of the present invention is to provide a method to form a flash memory device with optimized efficiency and high reliability.
A yet further object of the present invention is to provide a method to form a flash memory device where the key elements of the structure are self-aligned.
A yet further object of the present invention is to provide a flash memory cell with a dedicated erase gate.
A yet further object of the present invention is to provide an improved flash memory cell with an erase gate without increasing the cell size.
In accordance with the objects of this invention, a method to form control gates and erase gates for split-gate flash memory cells is achieved. The method comprises providing floating gates overlying a substrate. A control dielectric layer is formed overlying the floating gates and the substrate. A control conductor layer is formed overlying the control dielectric layer. Sidewall spacers are formed on the control conductor layer. The control conductor layer is partially etched down to create gaps between the sidewall spacers and the floating gates. The remaining control conductor layer forms control gates laterally adjacent to the floating gates. An isolating dielectric layer is formed overlying the control gates. An erase dielectric layer is formed lining the gaps and overlying the isolating dielectric layer. An erase conductor layer is deposited overlying the erase dielectric layer and isolating dielectric layer. The erase conductor layer is etched down to confine the remaining erase conductor layer to the gaps and to thereby form erase gates laterally adjacent to the floating gates.
Also in accordance with the objects of this invention, a split-gate flash memory device is achieved. The device comprises a floating gate overlying a substrate. A control gate is laterally adjacent to the floating gate and overlies the substrate. An erase gate is laterally adjacent to the floating gate and overlies the control gate. The erase gate is between a sidewall spacer and the floating gate.
REFERENCES:
patent: 6043530 (2000-03-01), Chang
Nhu David
Taiwan Semiconductor Manufacturing Co. Ltd.
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