Extended data output DRAM interface

Details Extended data output DRAM interface Extended data output DRAM interface

1995-06-06

1996-08-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 365233, G11C 700

Patent

active

055463444

ABSTRACT:
A DRAM interface, particularly for use in a video controller IC is provided with an improved technique for latching data from an extended data output (EDO) DRAM. An inactive column select CASn signal is fed back through the output of the DRAM interface, along with a write enable signal WEn, to emulate delays of such signals within the extended data output DRAM and the DRAm controller. The inactive CASn signal and write enable signal WEn are ANDed together to produce an ENABLE signal for latching data in a transparent latch. The use of the ENABLE signal optimizes the performance of the EDO DRAM and prevents collision of read and write data.

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