Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-27
2007-02-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S030000
Reexamination Certificate
active
10873242
ABSTRACT:
A method for correcting line width variation occurring during a development process in fabricating a photomask and a recording medium in which the exposure method is recorded is provided, wherein pattern line width variation occurring in a development process with respect to a desirable pattern is estimated, and a corrective exposure is performed using a dose or bias of an electron beam corresponding to the estimated pattern line width variation. Accordingly, pattern line width variation occurring during a development process can be reduced.
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Choi Ji-hyeon
Ki Won-tai
Yang Seung-hune
Bowers Brandon
Samsung Electronics Co,. Ltd.
Siek Vuthe
Volentine & Whitt P.L.L.C.
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