Executing multiple debug instructions

Details Executing multiple debug instructions Executing multiple debug instructions

1999-05-19

2002-01-29

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S036000, C712S034000, C714S030000, C714S018000, C714S727000, C714S726000, C714S729000, C713S601000

Reexamination Certificate

active

06343358

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including debug mechanisms where it is desired to execute multiple debug instructions.
2. Description of the Prior Art
It is known to provide data processing systems with debug mechanisms for assisting in the debugging of hardware and software. One known technique is to use JTAG serial scan chains to scan in instructions and data to be applied to the system being debugged. It is generally slow to scan in large numbers of instructions and data values via serial scan chains.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising:
a main processor;
an instruction transfer register for holding a data processing instruction and accessible via a first serial scan chain;
a data transfer register for holding a data value and accessible via a second serial scan chain;
debug logic for controlling said main processor, said instruction transfer register and said data transfer register such that a data processing instruction held within said instruction transfer register is passed a plurality of times to said main processor for execution upon a sequence of data values scanned into or from said data transfer register via said second serial scan chain.
The invention recognizes that in many circumstances the same instruction will be executed many times consecutively. In this circumstance, a significant increase in speed can be achieved by using separate scan chains for the instruction transfer and the data transfer whereby once the instruction has been scanned into place it can be left there and only the data values that change upon each execution need to be transferred via their separate scan chain. It will be appreciated that depending upon the particular instruction being executed, the data values may be transferred into the data transfer register or transferred out of the data transfer register.
Whilst the instruction being repeatedly executed could have many different forms, the present technique is particularly useful when the instruction is a memory access instruction. Memory access instructions often are repeatedly executed to provide block data transfers.
The implementation of the present technique is eased in embodiments in which the data transfer register is an addressable register that may be specified as an operand within one or more data processing instructions. In this way the degree of change required in the rest of the system to carry the present technique can be reduced.
Whilst the debug logic could have many forms it is preferred that the debug logic includes a debug coprocessor coupled to the main processor by a coprocessor interface.
In order to reduce potential data conflicts due to the main processor and the debug logic both trying to access the data transfer register at the same time, in preferred embodiments the data transfer register is in the form of two registers forming a bidirectional communications channel.
In preferred embodiments of the invention said data transfer register includes an instruction complete flag settable by said main processor for indicating that said data processing instruction has completed an execution iteration. In this way external debug circuitry may poll this flag after it has issued an instruction to determine when the instruction has completed and that it write more data to or read more data from the data transfer register. The scan chain controller may already be set to have the second serial scan selected as the active scan chain and so the polling can be quickly performed and a subsequent transfer will not require a change of active scan chain to be made.
As a way of increasing efficiency further, in preferred embodiments said second serial scan chain is operable to output bits of a data value to be transferred out of said data transfer register at the same time as storing bits of a data value to be transferred into said data transfer register. In this way each serial scan chain bit shift both loads in one bit of data and outputs one bit of data in a manner that reduces the time needed for transferring words of data into and out of the system.
Viewed from another aspect the present invention provides a method of processing data, said method comprising the steps of:
holding a data processing instruction accessible via a first serial scan chain in an instruction transfer register;
holding a data value and accessible via a second serial scan chain in a data transfer register;
controlling a main processor, said instruction transfer register and said data transfer register such that a data processing instruction held within said instruction transfer register is passed a plurality of times to said main processor for execution upon a sequence of data values scanned into or from said data transfer register via said second serial scan chain.


REFERENCES:
patent: 5297276 (1994-03-01), Millar et al.
patent: 5404359 (1995-04-01), Gillenwater et al.
patent: 5530504 (1996-06-01), Edgington
patent: 6073254 (2000-06-01), Whetsel
patent: 762 280 (1997-03-01), None
patent: 2 338 320 (1999-12-01), None

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