Executing debug instructions

Details Executing debug instructions Executing debug instructions

1999-05-19

2001-11-20

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C714S034000, C714S035000, C714S726000, C714S731000, C714S030000, C714S729000, C713S500000, C713S601000, C713S400000

Reexamination Certificate

active

06321329

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems incorporating debug mechanisms and the manner in which such systems execute debug instructions.
2. Description of the Prior Art
In order to facilitate the development of new data processing hardware and software it is known to provide dedicated debug mechanisms. Such mechanisms typically allow diagnostic data to be recovered and debug instructions to be executed, such as instructions to recover certain data values to locations from which they can be accessed as diagnostic data. In addition, it may be desired to execute particular instructions that use particular features or portions of the system being debugged to test the operation of those particular features or portions.
Some known data processing systems operate in the debug mode by switching to a different clock speed (typically slower) than the normal operation clock speed and then loading the desired instruction or instructions to be executed whilst remaining at the different clock speed. Whilst the different clock speed facilitates the loading of the instructions into the system (for example via a serial scan chain), it has the disadvantage that the instruction is not executed at its normal speed and so the value of the diagnostic operation is reduced.
Other known systems address this problem by loading the instructions at the different clock speed and then switching to the full clock speed for execution of that instruction before switching back to the different clock speed. Whilst this improves the accuracy and usefulness of the diagnostic operation, it has the disadvantage of requiring switching between clock speeds, clock synchronisation and their associated circuits.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising:
a main processor driven by a main processor clock signal at a main processor clock frequency;
debug logic at least a portion of which is driven by a debug clock signal at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal being asynchronous with said debug clock signal; and
an instruction transfer register into which a data processing instruction may be transferred by said debug logic and from which said data processing instruction may be read by said main processor; wherein
when switched from a normal mode to a debug mode said main processor continues to be driven by said main processor clock signal executing no-operation instructions until a data processing instruction is present within said instruction transfer register and said debug logic triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal.
The present invention recognises that the main processor can be left operating at its normal clock speed whilst instructions are loaded by arranging for the main processor to execute no-operations instructions pending the execution of the loaded instruction. When the loaded instruction is present within the instruction transfer register, it can then be issued to the main processor and executed at the normal clock speed without requiring clock switches or resynchronisation.
In the case where the main processor includes an instruction pipeline, preferred embodiments of the invention operate by the debug logic detecting that any pending instructions within the instruction pipeline when the debug mode was entered have drained from the instruction pipeline before the debug instruction is issued from the instruction transfer register and executed by the main processor.
Entry into the debug mode can the made in various different ways. Examples of these are execution of a breakpoint instruction commanding a switch to the debug mode, application of an external debug signal (similar to an interrupt), or the triggering of a programmed breakpoint or watchpoint.
A preferred mechanism for loading the instruction transfers register is via a serial scan chain. The way in which the main processor continues to operate at its normal clock speed executing no-operation instructions makes the provision of the serial scan chain mechanism simpler as it need not cater to the main processor.
As well passing data processing instructions to the main processor, in many cases it is also desirable to pass data values to the main processor. In order to facilitate this, a data transfer register is provided that may be accessed by both the debug logic operating at the debug clock frequency and the main processor operating at the main processor clock frequency.
This data transfer register may conveniently be accessed via a serial scan chain and may be split into the form of two data transfer registers to provide bidirectional communications whilst avoiding potential data conflicts.
Whilst at least a portion of the debug logic operates using the debug clock signal, in preferred embodiments the debug logic additionally includes a debug coprocessor coupled via a coprocessor interface to the main processor and operating using the main processor clock signal.
Viewed from another aspect the present invention provides a method of processing data, said method comprising the steps of:
driving a main processor with a main processor clock signal at a main processor clock frequency;
driving debug logic with a debug clock signal at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal being asynchronous with said debug clock signal;
transferring a data processing instruction into an instruction transfer register using said debug logic; and
reading said data processing instruction from said instruction transfer register using said main processor; wherein
when switched from a normal mode to a debug mode said main processor continues to be driven by said main processor clock signal executing no-operation instructions until a data processing instruction is present within said instruction transfer register and said debug logic triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal.


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patent: 5530804 (1996-06-01), Edgington et al.
patent: 6073254 (2000-06-01), Whetsel
patent: 0 762 280 (1997-03-01), None
patent: 2 337 834 (1999-12-01), None

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