Executing a translated block of instructions and branching...

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...

Reexamination Certificate

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C712S202000, C712S226000, C712S234000, C717S138000

Reexamination Certificate

active

09676175

ABSTRACT:
A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor architecture, wherein the translated first block of instructions operate with a stack of data entry positions. During the translation, an expected Top of Stack (TOS) position in the stack for the first block of code is generated.

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Flynn, Michael J., Computer Architecture, Pipelined and PArallel Processor Design, 1995, Jones and Bartlett Publishers, p. 492.

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