Exclusive Or/Nor circuit

Details Exclusive Or/Nor circuit Exclusive Or/Nor circuit

2001-12-05

2002-10-22

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Exclusive function

C326S113000, C326S121000

Reexamination Certificate

active

06469541

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital circuits, and more particularly to Hi Exclusive Or/Nor circuits configured to receive three or more inputs.
BACKGROUND
Digital electronic circuits are used in virtually every modem electronic system, such as computers, watches and telephones. Under continuous pressure from users for increased functionality from electronic systems, designers and manufacturers of digital electronic circuits constantly strive to reduce the size and increase the performance of their circuits. Even modest gains in the density and/or performance of a circuit become substantial if the circuit is repeated many times within a system.
Traditionally, digital logic functions have been implemented with a plurality of discrete logic circuits or gates. Two of the most important digital logic circuits are “Exclusive Or” circuits (also referred to herein as “XOR” circuits) and “Exclusive Nor” circuits (also referred to herein as “XNOR” circuits). An XOR circuit will produce a logical one if an odd number of inputs are a logical one. The XNOR logic function is the inverse of the XOR function. Thus, the XNOR function will produce a logical one if an even number of inputs are a logical one.
Logic functions such as XOR and XNOR may be represented by truth tables which define an output for each combination of inputs. The truth tables for a two-input and a three-input XOR function are shown below in Table 1a and 1b, respectively. A similar truth table may be constructed for a four-input XOR function, etc.
TABLE 1a
(two-input XOR)
I
0
I
1
O
0
0
0
0
1
1
1
0
1
1
1
0
TABLE 1b
(three-input XOR)
I
0
I
1
I
2
O
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Truth tables for a two-input and a three-input XNOR function are shown below in Table 2a and 2b, respectively. A similar truth table may be constructed for a four-input function, etc.
TABLE 2a
(two-input XNOR)
I
0
I
1
O
0
0
1
0
1
0
1
0
0
1
1
1
TABLE 2b
(three-input XNOR)
I
0
I
1
I
2
O
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
As can be seen from the truth tables above, a digital circuit adapted to perform an function can be modified to perform an XNOR function by adding an inverter to the output of the XOR circuit. Similarly, a digital circuit adapted to perform an XNOR function can be modified to perform an XOR function by adding an inverter to the output of the XNOR circuit.
In addition, a three-input XOR or XNOR circuit may be constructed by connecting a first two-input XOR or XNOR circuit in series with a second two-input XOR or XNOR circuit. For example, a three-input XOR circuit may be constructed from a pair of two-input XOR circuits connected in series, or from a pair of two-input XNOR circuits connected in series. A three-input XNOR circuit may be constructed from an XOR circuit connected in series with an XNOR circuit, or from an XNOR circuit connected in series with an XOR circuit.
XOR gates and XNOR gates are used in a wide variety of digital circuit applications including combinational logic, adder circuits, and parity checking. Many electronic systems have multiple XOR and XNOR gates. Therefore, any reduction in the size of XOR and/or XNOR gates may result in a substantial reduction in the size of such electronic systems. Similarly, any improvement in the performance of XOR and/or XNOR gates may result in a substantial improvement in the performance of such electronic systems.
SUMMARY OF THE INVENTION
The invention provides a digital circuit configured to receive three or more input signals and produce an output signal corresponding to either an XOR or XNOR of the input signals. In one embodiment of the invention, the circuit includes a first section connected in series with a second section to form a three-input XOR or XNOR gate. The first section is a two-input XOR or XNOR circuit having no more than eight transistors, including two transmission gate pairs. The second section is a two-input XOR or XNOR circuit having no more than six transistors, including one transmission gate pair. In an alternative embodiment, the circuit includes a plurality of first sections connected in series, with the last first section in the series connected to the second section to form an N-input XOR or XNOR gate.


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P. 295 of an article entitled “Ultra High Speed Digital Device Series, vol. 2: Ultra High Speed MOS Devices” edited by Susumu Koyama; published 1986.

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