Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-09-12
2002-10-15
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S207000, C365S210130
Reexamination Certificate
active
06466503
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC 119 based on Japanese Patent Applications P2000-292562 filed on Sep. 26, 2000, and P2001-253116 filed on Aug. 23, 2001, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory including current-draw-type memory cells, and particularly, to a technique of reading data from a semiconductor memory.
2. Description of the Related Art
Japanese Patent Laid Open Publication (Kokai) No. 2001-14880 discloses a masked ROM. This ROM has a memory cell array including bit lines, word lines intersecting the bit lines, and memory cells formed at the intersections of the word and bit lines. The memory cells of this technique are MOS transistors that are programmed with the use of masks.
There is a semiconductor memory having dummy cells (RMCs) whose sizes are designed to provide a current draw ability that produces a potential level lower than a potential level corresponding to data “1” to be stored in a memory cell (MC) and higher than a potential level corresponding to data “0” to be stored in the memory cell. For example, the current draw ability of the dummy cells is designed to provide a potential level half the data “1” potential level. In this case, a reference bit line (RBL) used when reading data from a memory cell provides an intermediate potential level between the data “0” and “1” potential levels to be read through a selected bit line (BL).
This technique above mentioned has some problems. The current draw ability of each dummy cell in a semiconductor memory must carefully be designed to precisely achieve a potential level half the data “1” potential level. If the current draw ability is inaccurate, it deteriorates the operation speed of the semiconductor memory.
To halve a current passing through a dummy cell with respect to a current passing through an ON memory cell, this technique controls the dummy cell itself. This involves difficult in designing and manufacturing work since precisely design the size and impurity concentration of each dummy cell is required. Namely, it is difficult to include the dummy cells of such high precision in a memory cell array in which memory cells are formed, and therefore, the related art separately forms the dummy cells from the memory cells. The separate configuration prohibits sense amplifiers from switching dummy and memory cells from one to another. This means that the related art must additionally prepare related circuits including sense amplifiers for the dummy cells.
When a given dummy cell passes a current (½ of I) that is half a current (I) passing through an ON memory cell, an operating potential level in a bit line that accesses the dummy cell is increased the specified level and stabilized at the level to serve as a reference potential level. To attain the stabilized potential level, the bit line needs a time, which becomes a wait time or precharge time on a sense amplifier. The precharge time deteriorates the speed of a memory cell read operation. To sense an OFF memory cell, a wait time is prolonged to the precharge time plus a sense margin.
SUMMARY OF THE INVENTION
An aspect of the present invention provides a semiconductor memory including a memory cell array including memory cells, a dummy cell array including dummy cells, a first bit line configured to pass one of a current representing data stored in a memory cell selected from the memory cell array or a current representing data stored in a dummy cell selected from the dummy cell array, a second bit line configured to pass the current representing the data stored in the selected dummy cell if the first bit line passes the current representing the data stored in the selected memory cell or the current representing the data stored in the selected memory cell if the first bit line passes the current representing the data stored in the selected dummy cell, a switching circuit configured to receive the currents passing through the first and second bit lines and provide an output current substantially half the current representing the data stored in the selected dummy cell and an output current equal to the current representing the data stored in the selected memory cell, and a sense amplifier configured to receive the output current substantially half the current representing the data stored in the selected dummy cell and the output current equal to the current representing the data stored in the selected memory cell and amplify those output currents.
Another aspect of the present invention provides a method of sensing data stored in a memory cell in a memory cell array with paired first and second bit lines, including dividing a current passing through the first bit line into two partial currents dividing a current passing through the second bit line into two partial currents if the current passing through the first bit line represents the data stored in the memory cell and if the current passing through the second bit line represents data stored in a dummy cell in a dummy cell array, providing a first output formed by recombining the partial currents from the first bit line, providing a second output formed by selecting one of the partial currents from the second bit line, and amplifying the first and second outputs, and if the current passing through the first bit line represents the data stored in the dummy cell and if the current passing through the second bit line represents the data stored in the memory cell, providing a third output formed by selecting one of the partial currents from the first bit line, providing a fourth output formed by recombining the partial currents from the second bit line, and amplifying the third and fourth outputs.
REFERENCES:
patent: 5148063 (1992-09-01), Hotta
patent: 5963484 (1999-10-01), Jung
patent: 6028791 (2000-02-01), Tanaka
patent: 6069831 (2000-05-01), Jang et al.
patent: 2001-14880 (2001-01-01), None
Koizumi Masayuki
Shibayama Hiroyuki
Kabushiki Kaisha Toshiba
Mai Son
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