Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-12
2002-12-24
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06498063
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention pertains to semiconductor fabrication processing and more particularly to a method for providing even nucleation between silicon and oxide surfaces for uniformly thin silicon nitride film growth used in semiconductor devices, such as dynamic random access memories (DRAMs).
In the manufacturing of dynamic random access memories (DRAMs), the size of the memory cell is the main contributing factor to the density and overall size of the device. A manufacturer of DRAMs has motivation to increase the storage capability, while maintaining the smallest die size possible, as the smaller die size results in a lower cost per device. As mentioned, the main contributor to the size of a memory device is the amount of space required for each storage cell that makes up the storage array. In that regard, DRAM fabrication engineers have focused on structures, on materials to make the structures and on methods to fabricate the structures necessary to make a storage cell.
To save space, the capacitor of the storage cell must reduce in size and yet maintain adequate capacitance to retain a sufficient charge during DRAM operation. There are several approaches to the capacitor design, for example trench capacitors formed in the substrate of a wafer or a stacked capacitor formed above the wafer substrate, to name two. Regardless of the design chosen, the size of the capacitor must be reduced and yet maintain sufficient capacitance as mentioned previously. Two of the main contributors to capacitance are the surface area of the capacitor plates and the dielectric quality of the insulator separating the capacitor plates. Major engineering efforts have gone into both areas.
In regards to dielectric quality, thin film dielectrics having high dielectric constant characteristics have emerged as the dielectric of choice, as the thinnest film that can be placed between the capacitor plates to prevent dielectric breakdown when a charge is present on the capacitor plates, drastically increases capacitance. With increased capacitance, the overall size of the capacitor can be reduced. However, thin film dielectrics present some challenges in fabricating the complete storage cell structure, which includes a storage cell access transistor and a storage capacitor.
One main challenge and a critical area of concern is oxidation punch through, which is important to avoid when forming thin film dielectrics. Oxidation punch through refers to the mechanism of atomic oxygen diffusing completely through a dielectric film. In the case of a capacitor cell dielectric, if oxidation punch through was allowed to occur a portion of an underlying diffusion region of an access transistor would become oxidized and thus diminish the transistor's operating characteristics. It is critical that oxidation punch through be at least reduced or ideally avoided altogether.
When dealing with thin film dielectrics, the dielectric film needs to be thick enough to sufficiently to reduce oxidation punch through. The minimum thickness of the dielectric film is dependent on the required oxidation time and temperature used and is particularly critical to maintain when using the dielectric film as a capacitor cell dielectric. It is also important that the dielectric film be a uniform film in order to minimize the overall thickness of the film.
One of the thin dielectric films of choice is nitride (i.e., silicon nitride) as nitride possesses sufficient dielectric constant characteristics and can be deposited as a very thin layer (less than 100 Å). However, a nitride film of this thickness is difficult to deposit uniformly on a surface that is made up of different types of material, especially materials that are not receptive to nitride deposition. When trying to deposit thin nitride films on different types of materials, the surface free energy involved in the deposition reaction is different for each of the different types of materials resulting in different incubation times. Because of the different incubation time for each material, uneven nucleation results thereby preventing the formation of a uniform dielectric film, particularly layers less than 100 Å.
Therefore, it is highly desirable to provide a process that solves the uneven nucleation between silicon and oxide surfaces in thin silicon nitride film growth used in semiconductor devices.
SUMMARY OF THE INVENTION
The present invention teaches a method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a single atomic layer of a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.
The above method can be applied to devices that would benefit from the use of a uniformly thin film layer, such as a memory device (i.e., DRAM, floating gate device, etc.) that operates by storing a charge. For example, one implementation of the present invention is to form a nitride dielectric layer that is less than 100 Å in thickness for the intended use as a storage capacitor dielectric.
These and other features and objects of the present invention will be apparent in light of the description of the invention embodied herein.
REFERENCES:
patent: 5445999 (1995-08-01), Thakur et al.
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6017791 (2000-01-01), Wang et al.
patent: 6046093 (2000-04-01), DeBoer et al.
patent: 6071771 (2000-06-01), Schuegraf
patent: 6143598 (2000-11-01), Martin et al.
patent: 6235571 (2001-05-01), Doan
patent: 6274899 (2001-08-01), Melnick et al.
Killworth, Gottman Hagan & Schaeff LLP
Micro)n Technology, Inc.
Nelms David
Nhu David
LandOfFree
Even nucleation between silicon and oxide surfaces for thin... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Even nucleation between silicon and oxide surfaces for thin..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Even nucleation between silicon and oxide surfaces for thin... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2932714