Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-08-21
2007-08-21
Tran, Binh X. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S702000, C438S718000, C438S719000, C438S738000
Reexamination Certificate
active
11240708
ABSTRACT:
The present invention is directed to a method of etching a multi-layer structure formed from a layer of a first material and a layer of a second material differing from the first material to obtain a desired degree of planarization. To that end, the method includes creating a first set of process conditions to etch the first material, generating a second set of process conditions to etch the second material; and establishing an additional set of process conditions to concurrently etch the first and second materials at substantially the same etch rate.
REFERENCES:
patent: 3795534 (1974-03-01), Mehalso et al.
patent: 4038110 (1977-07-01), Feng
patent: 4267212 (1981-05-01), Sakawaki
patent: 4389281 (1983-06-01), Anantha et al.
patent: 4426247 (1984-01-01), Tamamura et al.
patent: 4507331 (1985-03-01), Hiraoka
patent: 4657845 (1987-04-01), Frchet et al.
patent: 4665007 (1987-05-01), Cservak et al.
patent: 4692205 (1987-09-01), Sachdev et al.
patent: 4741926 (1988-05-01), White et al.
patent: 4794021 (1988-12-01), Potter
patent: 4891303 (1990-01-01), Garza et al.
patent: 4931351 (1990-06-01), McColgin et al.
patent: 4943516 (1990-07-01), Kamayachi et al.
patent: 4959252 (1990-09-01), Bonnebat et al.
patent: 4976818 (1990-12-01), Hashimoto et al.
patent: 5015602 (1991-05-01), Van Der Plas et al.
patent: 5071694 (1991-12-01), Uekita et al.
patent: 5110514 (1992-05-01), Soane
patent: 5173393 (1992-12-01), Sezi et al.
patent: 5198326 (1993-03-01), Hashimoto et al.
patent: 5212114 (1993-05-01), Grewal et al.
patent: 5234793 (1993-08-01), Sebald et al.
patent: 5240550 (1993-08-01), Boehnke et al.
patent: 5259926 (1993-11-01), Kuwabara et al.
patent: 5276126 (1994-01-01), Rogler
patent: 5314772 (1994-05-01), Kozicki et al.
patent: 5330883 (1994-07-01), Garza et al.
patent: 5434107 (1995-07-01), Paranjpe
patent: 5480047 (1996-01-01), Tanigawa et al.
patent: 5488007 (1996-01-01), Kim et al.
patent: 5545367 (1996-08-01), Bae et al.
patent: 5700626 (1997-12-01), Lee et al.
patent: 5743998 (1998-04-01), Park
patent: 5772905 (1998-06-01), Chou
patent: 5888650 (1999-03-01), Calhoun et al.
patent: 5893750 (1999-04-01), Hause et al.
patent: 5895263 (1999-04-01), Carter et al.
patent: 5905104 (1999-05-01), Eklund et al.
patent: 5907782 (1999-05-01), Wu
patent: 5954997 (1999-09-01), Kaufman et al.
patent: 5986330 (1999-11-01), Kalnitsky et al.
patent: 6033977 (2000-03-01), Gutsche et al.
patent: 6046056 (2000-04-01), Parce et al.
patent: 6074827 (2000-06-01), Nelson et al.
patent: 6096655 (2000-08-01), Lee et al.
patent: 6117798 (2000-09-01), Fang et al.
patent: 6232175 (2001-05-01), Liu et al.
patent: 6326627 (2001-12-01), Putvinski et al.
patent: 6329256 (2001-12-01), Ibok
patent: 6334960 (2002-01-01), Willson et al.
patent: 6342097 (2002-01-01), Terry et al.
patent: 6387787 (2002-05-01), Mancini et al.
patent: 6391798 (2002-05-01), DeFelice et al.
patent: 6426288 (2002-07-01), Meikle
patent: 6451703 (2002-09-01), Liu et al.
patent: 6455411 (2002-09-01), Jiang et al.
patent: 6468896 (2002-10-01), Rohr et al.
patent: 6517977 (2003-02-01), Resnick et al.
patent: 6562465 (2003-05-01), Nakashima et al.
patent: 6645879 (2003-11-01), Hong et al.
patent: 6703190 (2004-03-01), Elian et al.
patent: 6716767 (2004-04-01), Shih et al.
patent: 6719915 (2004-04-01), Willson et al.
patent: 6730256 (2004-05-01), Bloomstein et al.
patent: 6737202 (2004-05-01), Gehoski et al.
patent: 6743713 (2004-06-01), Mukher-Hee-Roy et al.
patent: 6767983 (2004-07-01), Fujiyama et al.
patent: 6777170 (2004-08-01), Bloomstein et al.
patent: 6814879 (2004-11-01), Shibata
patent: 6820677 (2004-11-01), Grinberg et al.
patent: 6893975 (2005-05-01), Yue et al.
patent: 6894245 (2005-05-01), Hoffman et al.
patent: 7041604 (2006-05-01), Miller et al.
patent: 2003/0129542 (2003-07-01), Shih et al.
patent: 2004/0029041 (2004-02-01), Shih et al.
patent: 2004/0029372 (2004-02-01), Jang et al.
patent: 2004/0029396 (2004-02-01), Zhang et al.
patent: 2004/0142501 (2004-07-01), Nakai et al.
patent: 2004/0188381 (2004-09-01), Sreenivasan
patent: 2004/0211754 (2004-10-01), Sreenivasan
patent: 2004/0224261 (2004-11-01), Resnick et al.
patent: 2004/0250945 (2004-12-01), Zheng et al.
patent: 2005/0199341 (2005-09-01), Delp et al.
patent: 2005/0253307 (2005-11-01), Sreenivasan
patent: 2005/0260848 (2005-11-01), Sreenivasan
patent: WO 2005/031299 (2005-04-01), None
patent: WO 2005/031855 (2005-04-01), None
Kotachi et al., Si-Containing Positive Resist for ArF Excimer Laser Lithography, Photopolymer Science and Technology, pp. 615-622 Nov. 4, 1995.
Haisma et al., Mold-assisted Nanolithography: A Process for Reliable Pattern Replication, J. Vac. Sci. Technol. B, pp. 4124-4128 Nov. 1, 1996.
Lin, Multi-Layer Resist Systems, Introduction to Microlithography, pp. 287-349 Feb. 14, 1983.
Nerac.com Retro Search, Reduction of Dimension of Contact Holes, Aug. 31, 2004.
Nerac.com Retro Search, Trim Etching of Features Formed on an Organic Layer, Sep. 2, 2004.
Luurtsema, Spin Coating for Rectangular Substrates, Retrieved May 23, 2002 from URL: http://buffy.eecs.berkelye.edu/IRO/Summary/97abstracts/gluurts.2.html May 23, 2002.
Photoresist Coating Methods, e-mail from Susan Bagen(BAGEN@aol.com) to Dhaval Shah Sep. 18, 1997.
Nakamatsu et al., Bilayer Resist Method for Room-Temperature Nanoimprint Lithography, Japanese Journal of Applied Physics, vol. 43, No. 6B, pp. 4050-4053 Jun. 29, 2004.
U.S. Appl. No. 10/946,565, naming Inventors Vidusek et al., entitled Method of Forming an In-Situ Recessed Structure, filed Sep. 21, 2004.
U.S. Appl. No. 10/946,577, naming Inventors Sreenivasan et al., entitled Reverse Tone Patterning on Surfaces Having Surface Planarity Pertubations, filed Sep. 21, 2004.
U.S. Appl. No. 10/946,566, naming Inventors Sreenivasan et al., entitled Pattern Reversal Employing Thick Residual Layers, filed Sep. 21, 2004.
U.S. Appl. No. 10/946,574, naming Inventors Stacey et al., entitled Patterning Substrates Employing Multi-Film Layers Defining Etch-Differential Interfaces, filed Sep. 21, 2004.
Data Sheet for MAK (Methyl n-Amyl Ketone), www.sp-chem.com/fine—e Jan. 1, 2003.
Data Sheet for gamma-Glycidoxypropyltrimethoxysilane, www.powerchemical.net/3100.htm Dec. 5, 2003.
Silicon or Silica, www.mii.org/Minerals/photosil Mar. 31, 2005.
Electronic Devices and Circuits, people.deas.harvard.edu/˜jones/es154/lectures/lecture—2/materials/materials.html Mar. 31, 2005.
Data Sheet for Cymel 303ULF, www.cytec.com, 2000.
Data Sheet for Cycat 4040, www.cytec.com, 1990.
International Chemical Safety Card for p-Toluenseulfonic Acid, www.itcilo.it/english/actrav/telearn/osh/ic/104154.htm Dec. 5, 2003.
Data Sheet for p-Toluenesulfonic Acid, NIOSH Manual of Analytical Methods (NMAM), Fourth Edition, 1998.
Data Sheet for Dow Corning Z-6018, no date.
Data Sheet for Methyl Amyl Ketone, www.arb.ca.gov/db/solvents/solvent—pages/Ketones-HTML/methyl—amyl.htm Mar. 31, 2005.
U.S. Appl. No. 11/184,664, naming Inventors LaBrake, entitled Method of controlling the critical dimension of structures formed on a substrate, filed Jul. 19, 2005.
Miller et al., Fabrication of Nanometer Sized Features on Non-Flat Substrates Using a Nano-Imprint Lithography Process, SPIE Microlithography Conference Feb. 1, 2005.
Stewart et al., Direct Imprinting of Dielectric Materials for Dual Damascene Processing, SPIE Microlithogrpahy Conference Feb. 1, 2003.
Smith et al., Employing Step and Flash Imprint Lithography for Gate Level Patterning of a MOSFET Device, SPIE Microlithography Conference Feb. 1, 2003.
Peurrung et al., Film Thickness Profiles over Topography in Spin Coating, J. Electrochem. Soc., vol. 138, No. 7 Jul. 1, 1991.
U.S. Appl. No. 11/240,707, naming Inventors Xu et al., entitled Deposition Technique to Planarize a Multi-Layer Structure, filed Sep. 30, 2005.
Wolf et al., Silicon Processing for the VLSI era, vol. 1; Process Technology, pp. 546-547 Jan. 1, 1986.
Wang David C.
Xu Frank Y.
Fish & Richardson P.C.
Kordzik Kelly K.
Molecular Imprints, Inc.
Tran Binh X.
LandOfFree
Etching technique to planarize a multi-layer structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Etching technique to planarize a multi-layer structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etching technique to planarize a multi-layer structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3895587