Etching process for high-k gate dielectrics

Details Etching process for high-k gate dielectrics Etching process for high-k gate dielectrics

2002-05-15

2004-11-16

Thai, Luan (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S785000

Reexamination Certificate

active

06818553

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to processes of etching high-k gate dielectric layers.
BACKGROUND OF THE INVENTION
High dielectric constant (high-k) dielectrics were thought to replace silicon oxide (SiO
2
) in the near future due to their low leakage current as compared to SiO
2
of the same equivalent oxide thickness (EOT). But there have been many problems in attempting to incorporate high-k dielectrics into the current complimentary metal-oxide semiconductor (CMOS) process flow such as thermal instability (the high-k material degrades under high temperature), transconductance, cross-contamination (metal out-diffusion from high-k dielectric metal oxides during thermal processes) and Gm/Idsat degradation (due to the presence of fixed charges and unstable high-k dielectric/poly-Si interface, mobility degradation of the MOS).
The high-k material has a slow etch rate compared to SiO
2
and further, the high-k gate dielectric reacts with the poly-Si gate to form an interfacial layer therebetween which is difficult to etch. In the high-k gate dielectric etching process, H
3
PO
4
and HF based chemical etches are not considered because of the concerns on poly-Si gate damage and shallow trench isolation (STI) over-loss (i.e. the STI will be over-etched as compared to the high-k gate dielectric layer). The present invention focuses upon these etching issues.
U.S. Pat. No. 6,271,094 B1 to Boyd et al. describes a high-k layer and gate patterning process.
U.S. Pat. No. 6,210,999 B1 to Gardner et al. describes a high-k gate dielectric and gate etch process.
U.S. Pat. No. 6,069,381 to Black et al. and U.S. Pat. No. 6,100,173 to Gardner et al. describe other high-k gate dielectric and gate patterning processes.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide a improved method of etching high-k gate dielectric layers.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a patterned gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.


REFERENCES:
patent: 6069381 (2000-05-01), Black et al.
patent: 6100173 (2000-08-01), Gardner et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6271094 (2001-08-01), Boyd et al.
patent: 6358810 (2002-03-01), Dornfest et al.
patent: 6451647 (2002-09-01), Yang et al.
patent: 6617210 (2003-09-01), Chau et al.
Van Zant, “Microchip Fabrication”, 4thed., pp. 120, 271.

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