Etching procedure for floating gate formation of a flash...

Details Etching procedure for floating gate formation of a flash... Etching procedure for floating gate formation of a flash...

2000-08-29

2003-01-21

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S266000, C438S267000, C438S593000, C438S260000, C438S264000

Reexamination Certificate

active

06509228

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to fabrication of flash memory devices, and more particularly to a method-for forming floating gates of the flash memory exhibiting improved contact reliability.
2. Description of the Prior Art
Field effect transistors having floating (unconnected) gates have long been utilized to form a non-volatile, semiconductor memory. Electrons are moved onto or removed from the floating gate of a given transistor memory cell in order to program or erase its state. The state of such a transistor memory cell is determined by applying a voltage across its source and drain and then measuring the current which passes through the transistor. The programmed level of charge on the floating gate is retained for a long period of time, essentially indefinitely. Memory arrays of such transistor cells are commonly available in various forms, such as PROMs, EPROMS, EEPROMs and flash EEPROMs. Currently, flash EEPROM technology is being used for large capacity semiconductor non-volatile memory, either in place of, or in combination with, a magnetic disk drive memory system.
Typically, such a semiconductor memory system is made up of a number of integrated circuit chips that each contain a two dimensional array of EEPROM cells, plus other integrated circuit chips providing a controller and other system operating support. One type of memory array integrated circuit chip includes elongated, spaced apart source and drain regions formed in a surface of a semiconductor substrate. These source and drain regions form the bit lines of the memory. A two dimensional array of floating gates has each floating gate positioned in a channel region between adjacent source and drain regions. An elongated control gate is positioned over each row of floating gates in a direction transverse to the source and drain regions. The control gates are the word lines of the memory array.
One type of cell used in such a memory array extends each of its floating gates over only part of its channel between the source and drain regions, while the control gate is positioned over the remaining portion of the channel. This is termed a “split-channel” type of EEPROM cell and effectively connects a select transistor in series with the floating gate transistor in order to isolate the floating gate transistor from the bit lines when its control gate (word line) is not active. An alternative type of EEPROM cell extends its control gate completely across the channel region, thus eliminating the select transistor and allowing the memory cell to be made smaller. However, the absence of the select transistor in each cell places additional constraints on operating a memory array of such cells.
One class of EEPROM devices employs an erase gate positioned adjacent the floating gate of each cell, with a thin dielectric therebetween, in order to transfer electrons from the floating gate to the erase gate when all the relative voltages are appropriately set. Flash EEPROM systems use a common erase gate for a sector or other block of cells, thus enabling their simultaneous erasure in a “flash.” An alternative class of EEPROM devices does not use the separate erase gate, but rather removes the electrons from the floating gate through the substrate when all the appropriate voltages are set. In such flash EEPROM systems, the sectors or other blocks of cells are isolated from one another on the substrate in order that the individual blocks may be selectively and individually erased.
Since a high density memory cell array is always desired, self-aligned techniques are used during manufacture of the circuit whenever possible. One way of forming an array with erase gates is to deposit the erase gates in between adjacent rows of memory cells that have already been largely formed, and to couple each erase gate with the floating gates of the adjacent rows on both sides.
FIG. 1
represents some relevant portions of a typical flash memory cell. The memory cell is formed on a semiconductor substrate
10
. Elongated, parallel source and drain regions (not shown) are implanted into a surface of the substrate
10
. Field oxide
20
has strips of doped polysilicon
30
(POLY
1
) extending across them. These polysilicon strips are then separated into separate floating gates. A gate oxide layer
22
(commonly referred to as the tunnel oxide) formed on the surface of the substrate
10
to separate the resulting floating gates from their respective memory cell channel portions of the substrate
10
. Doped polysilicon strips
40
(POLY
2
) arranged orthogonally with the polysilicon strips
30
, and also with the elongated source and drain regions, serve as control gates. An interpoly dielectric layer
32
overlies the floating gates
30
separates the control gates
40
from the floating gate
30
. Oxide strips
42
are formed over the top surface of the control gates to provide appropriate gate isolation. The side walls of the floating gates and the control gates are covered with oxide layers
34
and
44
respectively to insulate the floating gates
30
and control gates
40
from another doped polysilicon strips
50
(POLY
3
) that fills in the remaining space between the rows. The polysilicon strips
50
are formed into elongated erase gates and can be coupled through the tunnel dielectric
22
with the floating gates
30
.
FIGS. 2A-2D
shows process that is commonly used for forming the relevant portions of the floating gates
30
described above. Referring to
FIG.2A
, the gate oxide layer
22
is first thermally grown over the substrate
10
. Next, the POLY
1
layer
30
is formed followed by the deposition of the interpoly dielectric layer
32
. In order to define the floating gate structure and provide contact with the erase gates
50
of the memory, a vertical hole is etched through the interpoly dielectric
32
, the POLY
1
layer
30
and half-way through the tunnel oxide
22
. The etching generally takes place in a multi-chamber etch tool and achieved by performing layer etching in each layer's corresponding etch chamber. To remove the aforementioned interpoly dielectric
32
, polysilicon
30
and gate oxide
22
, the wafer is typically being transfered from one chamber to another. For example, the removal of the interpoly dielectric layer and the tunnel oxide layer is generally done by etching with a florinated chemistry such as CF
4
O
2
in an oxide chamber while the etching of the POLY
1
layer applies etchant such as HBrO
2
in a poly chamber. The alternations of the chamber applications thus result in three separate etching steps (First etching the interpoly dielectric
32
in an oxide chamber as indicated in FIG.
2
B. Then etching the POLY
1
layer
30
in a poly chamber as indicated in FIG.
2
C. Finally, etching the oxide layer
22
in an oxide chamber as indicated in
FIG.2D.
) for conventional floating gate definition.
The etching steps for forming the aforementioned vertical hole are conventionally done by reactive ion etching (RIE), which is an anisotropic dry etching process that is capable of forming clean vertical holes with high aspect ratios. However, upon the chamber transferring procedure, it is observed that recess areas often occur, especially on the border portions of the exposed POLY
1
and tunnel oxide, such as recess
33
indicated in FIG.
2
D. This is mainly due to the divergent chamber conditions, especially the pressure variations, amongst different etch chamber tools. In particular, the oxide chambers are generally equipped with a much higher pressure surrounding than the poly chambers. When the POLY
1
etching has been completed and the wafer is transferred from the poly chamber to the oxide chamber for the tunnel oxide etching, the abrupt increased etching pressure in the oxide chamber may cause the frontal etching area to over-etch and result in a recess with tapered shape profile, such as the recess
33
in the figure. Since surface recess of the contact hole could cause oxide thinning effect upon the subsequent oxide
34
f

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