Etching method for reducing bit line coupling in a DRAM

Details Etching method for reducing bit line coupling in a DRAM Etching method for reducing bit line coupling in a DRAM

1999-10-21

2001-11-06

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S743000

Reexamination Certificate

active

06312983

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to DRAM bit lines, and more particularly, to a method of etching an interlayer dielectric (ILD) that will reduce coupling between adjacent bit lines.
2. Background Information
As DRAMs become more highly integrated, the spacing between individual memory cells decreases. This causes many design and engineering challenges. One of the necessary steps in manufacturing a DRAM is the masking and etching of repetitively patterned interconnects, such as the bit line. The bit line, along with a word line, are the two primary control lines used to read and write to a DRAM memory cell. As the spacing between the typically parallel bit lines decreases, one effect is capacitive coupling between bit lines. One factor that has a large effect on the amount of capacitive coupling is the cross-sectional area of the bit line. For a dual damascene process, the width of the bit line is limited to the critical dimension of the photolithography process. Thus, at the photolithography limit, the cross-section of the bit line cannot be reduced further.
Therefore, what is needed is a method to manufacture bit lines having a reduced cross-section while using photolithography techniques that are currently in use today.
SUMMARY OF THE INVENTION
A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching said interlayer dielectric to form trenches in said interlayer dielectric, said trenches collectively forming a bit line pattern, said trenches having tapered side walls; and depositing a conductive material into said trenches to form said bit line.


REFERENCES:
patent: 5294561 (1994-03-01), Tanigawa et al.
patent: 5422295 (1995-06-01), Choi et al.
patent: 5746884 (1998-05-01), Gupta et al.
patent: 5998251 (1999-12-01), Wu et al.
patent: 6040247 (2000-03-01), Chung

Affiliated with

Also associated with

Rating

Etching method for reducing bit line coupling in a DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Etching method for reducing bit line coupling in a DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etching method for reducing bit line coupling in a DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2570081