Etch residue reduction by ash methodology

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S637000, C438S638000, C438S639000, C438S642000, C438S643000, C438S645000, C438S710000, C438S734000, C257SE21579, C257SE21029, C257SE21257

Reexamination Certificate

active

07910477

ABSTRACT:
Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

REFERENCES:
patent: 6323121 (2001-11-01), Liu et al.
patent: 6362093 (2002-03-01), Jang et al.
patent: 6399483 (2002-06-01), Liu et al.
patent: 6582974 (2003-06-01), Lui et al.
patent: 6727185 (2004-04-01), Smith et al.
patent: 7015149 (2006-03-01), Woo
patent: 7033944 (2006-04-01), Park et al.
patent: 7094688 (2006-08-01), Oryoji
patent: 7169440 (2007-01-01), Balasubramaniam et al.
patent: 7192877 (2007-03-01), Ali
patent: 7192878 (2007-03-01), Weng et al.
patent: 7344992 (2008-03-01), Choi
patent: 2003/0170993 (2003-09-01), Nagahara et al.
patent: 2003/0192856 (2003-10-01), Balasubramaniam et al.
patent: 2003/0224595 (2003-12-01), Smith et al.
patent: 2004/0063306 (2004-04-01), Takeuchi
patent: 2004/0127016 (2004-07-01), Hoog et al.
patent: 2005/0045206 (2005-03-01), Smith et al.
patent: 2005/0079405 (2005-04-01), Enomoto et al.
patent: 2005/0079717 (2005-04-01), Savas et al.
patent: 2005/0101125 (2005-05-01), Smith et al.
patent: 2005/0142855 (2005-06-01), Choi
patent: 2006/0000804 (2006-01-01), Oyama et al.
patent: 2006/0094221 (2006-05-01), Soda et al.
patent: 2007/0184666 (2007-08-01), Smith et al.
patent: 2007/0224825 (2007-09-01), Xiao et al.
“Metal Hardmask Etch Residue Removal for Advanced Copper / Low-k Devices”, Hua Cui, Simon J. Kirk and David Maloney, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 366-370.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Etch residue reduction by ash methodology does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Etch residue reduction by ash methodology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etch residue reduction by ash methodology will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2662673

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.