Etch recipe for embedded DRAM passivation with etch stopping lay

Details Etch recipe for embedded DRAM passivation with etch stopping lay Etch recipe for embedded DRAM passivation with etch stopping lay

1998-04-06

1999-11-23

Schilling, Richard L.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430317, 216 6, 216 41, 216 67, 216 72, 438714, 438738, G03F 740, B44C 122, C25F 300, C03C 1500

Patent

active

059897848

ABSTRACT:
A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85. The method comprises: forming fuses 16 over said isolation regions 10 over the fuse area 15; forming a first dielectric layer 30 overlying the fuses 16; forming an etch stop layer 40 over the first dielectric layer 30; forming an insulating layer 43 over the etch stop layer; forming a fuse opening 92 in the insulating layer 43 by etching, in a first etch stage, thorough fuse photoresist openings 90A and stopping the first etch stage on the etch stop layer 40; and etching though the etch stop layer 40 in the fuse opening 92 in a second etch stage.

REFERENCES:
patent: 4997789 (1991-03-01), Keller et al.
patent: 5256597 (1993-10-01), Gambino
patent: 5292677 (1994-03-01), Dennison
patent: 5536678 (1996-07-01), Peek

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