Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-08-23
2004-07-13
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S710000, C438S723000, C438S743000, C216S067000
Reexamination Certificate
active
06762127
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to etch processes, materials and devices for plasma etching C-doped silicon oxide, such as oxidized organo silane compounds, to form dielectric materials and in particular to etch processes of these dielectric materials that provide improved etch selectivity to silicon oxide and organic photoresist.
BACKGROUND OF THE INVENTION
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device's external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form horizontal connections between electronic circuit elements while conductive via plugs form vertical connections between the electronic circuit elements, resulting in layered connections.
A variety of techniques are employed to create interconnect lines and via plugs. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneously filled with a conductor material, for example a metal, thus simultaneously forming an interconnect line and an underlying via plug. Examples of conventional dual damascene fabrication techniques are disclosed in Kaanta et al., “Dual Damascene: A ULSI Wiring Technology”, Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152 and in U.S. Pat. No. 5,635,423 to Huang et al., 1997.
An example of a prior art dual damascene technique is illustrated in
FIGS. 1A-1C
, showing various IC structures. As depicted in
FIG. 1A
, a dielectric layer
110
is deposited on a semiconductor substrate
112
. An etch mask
116
, having a via pattern
118
, is positioned on dielectric layer
110
. A timed anisotropic etch is utilized to etch a hole
120
in layer
110
conforming to the via pattern. Mask
116
is subsequently replaced by mask
122
(
FIG. 1B
) having a trench pattern
124
. A timed anisotropic etch is used to form trench
126
and to simultaneously deepen hole
120
to form via hole
128
. This via hole can be etched to expose semiconductor substrate
112
. Alternatively, the via hole can be over-etched partly into the substrate. As illustrated in
FIG. 1C
, the via hole and trench are then filled simultaneously with a suitable metal
130
. Metal
130
thus forms a metallized interconnect line
132
and a via plug
134
that is in contact with semiconductor substrate
112
. Additionally, a liner or barrier layer may be deposited inside the via hole and the trench prior to deposition of the interconnect metal and the via plug. The surface of layer
110
is planarized to remove excess metal
130
and to define interconnect line
132
. Alternatively, metal etch-back can be utilized to define the line.
As described above in connection with etching hole
120
and trench
126
, a timed etch procedure is required to form dual damascene structures exemplified by
FIGS. 1A-1C
. However, it is well known to those of ordinary skill in the art that timed etching techniques are not well suited for reliably forming holes of a predetermined depth. For example, a timed etch of holes across a semiconductor wafer can result in significant depth variations of holes across the wafer, particularly for 200 mm and 300 mm wafers. These depth variations can result in rejected semiconductor products that fail product specifications.
An example of prior art dual damascene that does not utilize a timed etch technique is shown in IC structures illustrated in
FIGS. 2A-2C
. As depicted in
FIG. 2A
, a first dielectric layer
210
is deposited on a semiconductor substrate
212
. An etch stop layer
216
, is deposited on first dielectric layer
210
. A second dielectric layer
218
is deposited on etch stop
216
, and an etch mask
220
is positioned on dielectric layer
218
. Etch mask
220
is patterned (
221
) for etching a via hole. Second dielectric layer
218
is etched using a first anisotropic etch procedure, to form a hole
222
(
FIG. 2A
) conforming to the via pattern. This etching procedure is stopped at etch stop layer
216
, by using an etch chemistry that is selective to the etch stop layer. Etch mask
220
is removed and another etch mask
224
(see,
FIG. 2B
) is positioned on second dielectric layer
218
such that it is patterned (
226
) for forming a trench. A second anisotropic etch procedure is used to etch trench
228
in layer
218
. Simultaneously, hole
222
is extended to substrate
212
, by etching through etch stop layer
216
and through first dielectric layer
210
. In this dual damascene technique the first etch procedure has a greater selectivity to etch stop layer
216
than the second etch procedure. As shown in
FIG. 2B
, the second etch procedure results in forming trench
228
and via hole
230
, that extends to semiconductor substrate
212
. Mask
224
is removed, after which trench
228
and via hole
230
are simultaneously filled with a suitable conductive metal
232
(see,
FIG. 2C
) forming metallized line
234
and via plug
236
that contacts substrate
212
. Excess metal
232
is removed from the surface of layer
218
to define line
234
.
The techniques described in connection with
FIGS. 2A-2C
utilize an etch stop layer rather than a timed etch. Dielectric layers, such as layers
210
and
218
shown in
FIGS. 2A-2C
typically include materials that have a low dielectric constant such as silicon oxide and related silica glasses as well as dielectric polymeric materials. Etch stop layers include silicon nitrides such as Si
3
N
4
. The typical etch stop layer materials have a significantly higher dielectric constant than the materials utilized in the dielectric layers. It is known that the higher dielectric constant of these etch stop materials is disadvantageous because it can result in capacitive coupling between adjacent metal lines, that can lead to cross talk and/or RC (resistance coupling) delay that degrades the overall performance of the IC.
It is known to form dual damascene structures wherein one of the dielectric layers includes a SiO
x
material such as SiO
2
or a silicon glass while the other dielectric layer comprises a dielectric material having a lower dielectric constant than SiO
x
. This combination can result in a combined dielectric structure having an improved, i.e. lower, dielectric constant as compared with a structure wherein both layers include SiO
x
. Dielectric materials having a lower dielectric constant than SiO
x
include C-doped silicon oxide materials, such as oxidized organo silane materials that are formed by partial oxidation of an organo silane compound, such that the dielectric material includes a carbon content of at least 1% by atomic weight, as described in U.S. Pat. Nos. 6,072,227 (Yau et al., 2000) and 6,054,379 (Yau et al., 2000) and U.S. Pat. application Ser. No. 09/553,461 which was filed Apr. 19, 2000, a continuation-in-part of U.S. Pat. No. 6,054,379. Commonly assigned U.S. Pat. Nos. 6,072,227 and 6,054,379, and U.S. Pat. application Ser. No. 09/553,461 are herein incorporated by reference in their entireties.
The oxidized organo silane materials, described in the '227 and '379 patents and the '461 patent application, are formed by incomplete or partial oxidation of organo silane compounds generally including the structure:
In this structure, —C— is included in an orga
Boiteux Yves Pierre
Chen Hui
Gregoratto Ivano
Hsieh Chang-Lin
Hung Hoiman
Bach Joseph
Dalhuisen Albert J.
Hiteshew Felisa
LandOfFree
Etch process for dielectric materials comprising oxidized... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Etch process for dielectric materials comprising oxidized..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etch process for dielectric materials comprising oxidized... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3257432