Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-09-14
1999-02-02
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438396, H01L 218242, H01L 2120
Patent
active
058664530
ABSTRACT:
An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.
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Doan Trung
Fazan Pierre
Lowrey Tyler
Prall Kirk D.
Bowers Charles
Micro)n Technology, Inc.
Thomas Toniae M.
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