Etch bias distribution across semiconductor wafer

Details Etch bias distribution across semiconductor wafer Etch bias distribution across semiconductor wafer

1998-12-01

2001-07-17

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C438S014000

Reexamination Certificate

active

06262435

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the production of semiconductor wafers and test wafers used in developing the semiconductor wafer. In particular, the present invention relates to reducing variations in the etch bias and slope profile of structures formed at various locations across the test wafer.
BACKGROUND OF THE INVENTION
Integrated circuits are formed on semiconductor wafers typically made from silicon. The wafers are substantially round and typically have a diameter of approximately six to eight inches. Since a single integrated circuit die is often no more than 1 cm
2
, a great many integrated circuit die can be formed on a single semiconductor wafer. After the semiconductor wafer has been processed to form a number of integrated circuit die on its surface, the wafer is cut along “scribe lines” to separate the integrated circuit die for subsequent packaging and use.
Formation of integrated circuits on the wafer is accomplished using photo-lithography. In general, lithography refers to processes for pattern transfer between various media. The basic photo-lithography system consists of a light source, a photomask (also known as “reticle”) containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask.
Exposing a resist on the wafer to light of an appropriate wavelength through the reticle causes modifications in the molecular structure of the resist polymers to allow for transfer of the pattern from the photomask to the resist. The modification to the molecular structure allows a resist developer to dissolve and remove the resist in the exposed areas, presuming a positive resist is used. If a negative resist is used, the developer removes the resist in the unexposed areas.
Once the resist on the wafer has been developed, one or more etching steps take place which ultimately allow for transferring the desired pattern to the wafer. For example, in order to etch a device feature layer disposed between the resist and substrate, an etchant is applied over the patterned resist. The etchant comes into contact with the underlying feature layer by passing through the openings in the resist formed during the resist exposure and development steps. Thus, the etchant serves to etch away those regions of the feature layer which correspond to the openings in the resist, thereby effectively transferring the pattern in the resist to the feature layer. In subsequent steps, the resist is removed and another etchant may be applied over the patterned feature layer to transfer the pattern to the wafer or another layer in a similar manner.
The resolution of an etching process is a measure of the accuracy of pattern transfer, which can be quantified by an etch bias quantity. Bias refers to the difference in lateral dimension between the etched image and the mask image. In the formula most commonly used at present, two parameters give the bias according to the equation B=(d
m
−d
f
), where B stands for the etch bias, d
m
is the length of a particular critical dimension (CD) as measured along the mask image made in the resist before any etching of the device feature layer, and d
f
represents the final length of the CD measured along the bottom surface of the etched layer.
A zero-bias process produces a vertical edge profile coincident with the edge of the mask. In other words the etched device feature layer and the patterned resist would all be precisely aligned. In this case, there is no etching of the device feature layer or the resist in the lateral direction, and the pattern is perfectly transferred. This case represents the extreme of anisotropic etching. Achieving an anisotropic etch can be very important in the manufacture of some devices. However, as a practical matter, a perfectly anisotropic etch is difficult to achieve in many instances.
Referring now to
FIGS. 1
a
-
1
c
, the concept of etch bias is shown in more detail.
FIG. 1
a
depicts a semiconductor device
20
under construction having a device feature layer
24
which has been formed upon semiconductor substrate
22
. Previous to this step, a photoresist layer
28
has been formed over the device feature layer
24
and patterned by well-known photolithographic means, and the photoresist
28
has a dimension of d
m
which is measured from above.
At this stage, the physical or chemical etch of the device feature layer
24
is ready to occur. This etching gives a structure such as that seen in
FIG. 1
b
, viewed from above, where the device feature layer
24
has been formed having the dimension d
f
, which is reduced from the dm dimension. From
FIG. 1
b
, the etch bias may be taken as B=(d
m
−d
f
). The dimension of d
m
, shown in
FIG. 1
b
is presented for comparison purposes only.
FIG. 1
c
illustrates in profile the result of etching the feature layer
24
depicted in
FIG. 1
b
in which a measurable etch bias exists. As can be seen, following etching, the feature layer
24
includes sloped edges
26
due to the imperfect anisotropic etch. The sloped edges
26
define a slope profile or slope effect of the feature layer
24
which is proportional to the etch bias.
While eliminating etch bias and minimizing the slope effect is of concern, the ability to anticipate the effect that the etch bias and slope profile will have on a final integrated circuit is also of significant importance. For example, during development of wafers, often times test die and test circuits are produced so that discrete functions may be tested prior to development of a final wafer. For example, for a single die on a final wafer there may be on the order of twenty test die produced on test wafers prior to integrating the desired circuit onto the final wafer. During production and testing of these test die, it is advantageous to measure the etch bias and slope profile on the structures created so that appropriate calculations can be made as to how these may effect the final wafer. Hereinafter, “structures” shall refer to any line or other formation etched into or onto a test wafer or final wafer. By having advanced knowledge regarding the expected critical dimensions of a given structure, the ability to integrate such a structure into a wafer without interfering with adjacent lines can be better accessed. As etch bias, slope effect, and other critical dimension measurements made during the testing phase play a significant factor in determining the overall integration of the final wafer structure, accurate and representative measurements are highly desirable.
SUMMARY OF THE INVENTION
It has been observed that the critical dimensions of structures produced on a test wafer vary depending on whether the structure in located in a densely populated area of the wafer or a sparsely populated area of the wafer. For instance, as a result of etching, structures located in densely populated regions of a wafer were found to have a smaller etch bias than those structures located in sparsely populated areas. Because final wafers ultimately formed from the test wafers are highly integrated and have a dense population of circuits, such wafers typically do not include sparsely populated regions as in the test wafers. Accordingly, conventional critical dimension measurements of those structures located in sparsely populated regions of a test wafer do not always provide accurate and representative data regarding what the critical dimensions of such structures will be when integrated into a densely populated region.
The present invention relates to a method and apparatus for controlling the critical dimensions of those structures produced on sparsely populated areas of a test wafer so they more accurately depict the actual critical dimensions found for such structures on a densely populated final wafer. In order to do so, the present invention provides for adding dummy structures on a test reticle in those areas having sparsely populated test circuits. In this manner, the test wafer will be formed having uniformly densely populated r

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