Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-05-15
1998-09-29
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438723, 438743, 216 38, 216 80, H01L 2100
Patent
active
058145648
ABSTRACT:
The present invention provides a method of to planarize a spin-on-glass layer overlying a HDP-CVD oxide layer using a six etchback process. The process comprises: forming a spin-on-glass layer 40 over a plasma chemical vapor deposition (HDP-CVD)oxide layer 30 over spaced raised portions 20 on a semiconductor structure. The spin-on-glass and the density plasma chemical vapor deposition (HDP-CVD) oxide layer 30 are then planarized using a six etch back process comprising: Step 2, (Etch High), a CF4 gas flow of between about 88 and 108 sccm, CHF.sub.3 flow between about 35 and 45 sccm, an argon flow of between about 40 and 60 sccm, at a pressure of between about 210 and 310 mtorr, at a power of between 650 and 950 watts; Step 3 (Etch Low) a CF4 gas flow of between about 10 and 20 sccm, CHF.sub.3 flow between about 70 and 90 sccm, an argon flow of between about 40 and 60 sccm, at a pressure between about 210 and 310 mtorr, and at a power of between 750 and 1050 watts, and for a time between about 70 and 110 seconds; Step 4 a Sputter step; and Step 5 a Plasma O.sub.2 clean step.
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patent: 5461010 (1995-10-01), Chen et al.
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patent: 5679211 (1997-10-01), Huang
Chang Tony
Chung Bu-Chin
Rau Ruey-Feng
Yao Liang-Gi
Ackerman Stephen B.
Powell William
Saile George O.
Stoffel William J.
Vanguard International Semiconductor Corporation
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