ESD protection with uniform substrate bias

Details ESD protection with uniform substrate bias ESD protection with uniform substrate bias

2005-05-31

2005-05-31

Sherry, Michael (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C257S355000

Reexamination Certificate

active

06900969

ABSTRACT:
Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.

REFERENCES:
patent: 5714784 (1998-02-01), Ker et al.
patent: 5838050 (1998-11-01), Ker et al.
patent: 5940258 (1999-08-01), Duvvury
patent: 6249413 (2001-06-01), Duvvury
patent: 6274909 (2001-08-01), Chang et al.

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