Memory device capable of performing high speed reading while...

Details Memory device capable of performing high speed reading while... Memory device capable of performing high speed reading while...

2005-05-17

2005-05-17

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S200000

Reexamination Certificate

active

06894922

ABSTRACT:
When normal bit lines BL3and /BL3are selected, spare bit lines SBL2and /SBL2are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals φ1and φ2given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals φ1and φ2so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.

REFERENCES:
patent: 6760244 (2004-07-01), Yamada
patent: 20020071308 (2002-06-01), Muranaka et al.
R. Scheuerlein et al., “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, 2000 IEEE ISSCC Digest of Technical Papers, TA7.2, Feb. 2000, pp. 94-95, 128-129, 409-410.
M. Durlam et al., “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, 2000 IEEE ISSCC Digest of Technical Papers TA 7.3, pp. 96-97, 130-131, 410-411.
P.K. Naji et al., “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, 2001 IEEE ISSCC Digest of Technical papers, TA7.6, Feb. 2001, pp. 94-95, 122-123, 404-405.

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