ESD protection using selective siliciding techniques

Details ESD protection using selective siliciding techniques ESD protection using selective siliciding techniques

1998-02-26

1999-12-21

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438233, 438586, H01L 218238

Patent

active

060048387

ABSTRACT:
The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined discharge paths are created for discharging input and output buffer pads, during an ESD event, through ESD protection devices. During fabrication, an oxide layer is utilized as a mask to prevent silicided regions from forming in source/drain regions, self-aligned with the gates. The buffer transistor gate-to-contact spacing is made longer than the gate-to-contact spacing in the associated protection transistor, to shunt charge through the protection device. In a further embodiment, active area resistance is formed between the output/input buffer transistor and the ESD protection device, to further increase the resistance of the path between the buffer pad to the associated buffer transistor.

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