ESD protection device with FET circuit

Details ESD protection device with FET circuit ESD protection device with FET circuit

1995-02-13

1996-10-08

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

361 56, 361 91, 361212, 257360, H02H 904, H01L 2362

Patent

active

055635253

ABSTRACT:
An FET is connected between ground and a pad to be protected from an ESD voltage, and when an ESD voltage appears at the pad the drain-channel junction breaks down and produces hole-electron pairs that turn on a parasitic bipolar transistor which clamps the voltage at the pad. A resistor connects the gate of the FET to ground. As the ESD voltage rises at the pad, the gate to drain capacitance charges in circuit with the resistor. The voltage across the gate oxide rises slowly enough that the FET is enabled to produce hole-electron pairs for turning on the bipolar transistor before the oxide voltage has reached a value that might damage the gate oxide.

REFERENCES:
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Weste et al.; "Principles of CMOS VLSI Design, A Systems Perspective", .COPYRGT.1985, by AT&T Bell Laboratories and Kamran Eshraghian; p. 59.
Weste et al.; "Principles of CMOS VLSI Design, A Systems Perspective"; .COPYRGT. 1985 by AT&T Bell Laboratorires, Inc. and Kamran Eshraghian; p. 58.

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