Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-21
2002-06-04
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S157000, C438S396000, C438S585000
Reexamination Certificate
active
06399431
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an electrostatic discharge device using silicon-on-insulator (SOI) technology in the fabrication of integrated circuits.
(2) Description of the Prior Art
Electrostatic discharge (ESD) refers to a high voltage accidentally applied to an integrated circuit. ESD can result from either automated or human handling. If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. MOSFET devices are particularly vulnerable to ESD damage. Because of this danger, ESD protection transistors are fabricated to direct ESD current away from the circuit it is protecting.
An isolation technology that depends on completely surrounding devices by an insulator is referred to as silicon-on-insulator (SOI) technology. In general, the advantages of SOI technology include simple fabrication sequence, reduced capacitive coupling between circuit elements, and increased packing density. The SOI technology is discussed in
Silicon Processing for the VLSI Era
, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 66-67. The SOI process technology presents a challenge to ESD protection because the presence of the insulator layer (I) sandwiched between the two silicon layers prevents discharging of charges. This may lead to more severe ESD. The present invention overcomes these challenges and uses silicon-on-insulator (SOI) technology to make an electrostatic discharge (ESD) device.
A number of patents present a variety of methods to form ESD devices. U.S. Pat. No. 5,585,299 to Hsu shows a process for forming ESD and FET devices using selective masking processes. U.S. Pat. No. 5,141,898 to Lapham shows a ESD device having a thick oxide formed at low temperature. U.S. Pat. No. 5,674,761 to Chang et al discloses a P/N diode ESD device. None of these patents show an ESD device using SOI technology.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for forming an electrostatic discharge device in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming an electrostatic discharge device using silicon-on-insulator technology.
In accordance with the objects of the invention, a method for forming an electrostatic discharge device using silicon-on-insulator technology is achieved. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form gate electrodes wherein the semiconductor substrate is exposed between two of the gate electrodes. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to one of the gate electrodes. Spacers are formed on sidewalls of the gate electrodes. An interlevel dielectric layer is deposited overlying the gate electrodes. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device in the fabrication of integrated circuits.
REFERENCES:
patent: 5141898 (1992-08-01), Lapham
patent: 5166084 (1992-11-01), Pfiester
patent: 5389566 (1995-02-01), Lage
patent: 5585299 (1996-12-01), Hsu
patent: 5674761 (1997-10-01), Chang et al.
patent: 5716875 (1998-02-01), Jones, Jr. et al.
patent: 5821160 (1998-10-01), Rodriguez et al.
patent: 5872041 (1999-02-01), Lee et al.
patent: 5898619 (1999-04-01), Chang et al.
patent: 5949706 (1999-09-01), Chang et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 6004837 (1999-12-01), Gambino et al.
patent: 6010927 (2000-01-01), Jones, Jr. et al.
patent: 6238967 (2001-05-01), Shiho et al.
patent: 02000311951 (2000-11-01), None
S. Wolf, “Silicon Processing for the VLSI Era”, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, c. 1990, pp. 66-67.
Ang Ting Cheong
Loong Sang Yee
Quek Shyue Fong
Song Jun
Chartered Semiconductor Manufacturing Ltd.
Chaudhuri Olik
Pike Rosemary L.S.
Saile George O.
Schillinger Laura M
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