ESD protection circuit with field transistor clamp and resistor

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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361 56, 361 91, 361212, 257360, H02H 904, H01L 2362

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active

055657907

ABSTRACT:
An improved ESD protection circuit of the type having a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and a node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.

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patent: 5477407 (1995-12-01), Kobayashi et al.
Weste et al.; "Principles of CMOS VLSI Design, A Systems Perspective"; .COPYRGT.1985 by AT&T Bell Laboratories, Inc. and Kamran Eshraghian; pp. 58 and 59.

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