ESD implantation method in deep-submicron CMOS technology...

Details ESD implantation method in deep-submicron CMOS technology... ESD implantation method in deep-submicron CMOS technology...

2001-10-05

2003-02-04

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S305000, C438S301000, C438S199000

Reexamination Certificate

active

06514839

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to methods and apparatus for protection of semiconductor devices from electrostatic discharge damage.
2. Description of Related Art
ESD (electrostatic discharge) damage has become one of the main reliability concerns on the IC (integrated circuit) products. Especially, while the CMOS technology is developed into the deep-submicron regime, the scaled-down MOS devices and thinner gate oxide become more vulnerable to ESD stress. For general industrial specification, the input and output pins of the IC products have to sustain the human-body-model ESD stress of above 2000V. Thus, the ESD protection circuits have to be placed around the input and output pads of the IC devices to protect the IC devices against the ESD damage.
In the deep-submicron CMOS technology, the short-channel NMOS device (also PMOS device) has the Lightly Doped Drain (LDD) structure to overcome the hot-carrier effect. The LDD structure also generates a peak structure at the drain region, which closes to the surface channel. When such an NMOS device is stressed by a positive ESD voltage, the ESD current is focused and discharged through the LDD peak of the NMOS device structure. Because the LDD peak is the nearest region close to the grounded source, the first breakdown on the drain of the NMOS device happens at this LDD peak region. So, the LDD region with a far shallower junction depth is easily damaged by the ESD current to cause a far lower ESD level on the output NMOS device.
To improve the ESD level of the output NMOS device, one method is to remove the LDD peak from the output NMOS device. An output NMOS device, which has no LDD peak structure in its drain region, can sustain a far higher ESD level. The traditional method is to add an extra ESD-implantation process step into the CMOS process flow with an additional mask layer to make the output NMOS device having no LDD peak structure. The process of making such an NMOS device without LDD peak structure had been reported in some US patents, which are listed in references [
1
-
7
] below.
One typical method of such prior art is shown in
FIG. 1
which is a flowchart of a process referred to herein as “the Prior Art I” process.
FIGS. 2A-2H
show cross-sectional views of the process flow of the Prior Art I process of FIG.
1
. In
FIGS. 2A-2H
, the ESD protection devices are shown as the left-hand portions of the drawings and the internal devices are shown as the right-hand portions of the drawings.
The first step is to provide a substrate with a silicon oxide layer. The next step is to form a gate-oxide layer and a gate electrode layer of doped conductive polysilicon (poly) that is patterned into gate electrodes. That is followed by a self-aligned LDD implantation aside from the gate electrodes. A Heavily Doped ESD Implantation follows. Then cover with a Low-Temperature Oxide (LTO) and form sidewall spacers adjacent to the gate electrodes followed by a CMOS N+ Diffusion Implantation step. A CMOS P+ Diffusion Implantation step follows. A CVD LTO process deposits silicon oxide followed by contact hole etching.
FIG. 2A
shows a cross-sectional views of a silicon semiconductor substrate in which a P-well doped with P type dopant has been formed with FOX (field oxide) regions at each end of an ESD Protection Device on the left and an Internal device formed on the right with intermediate portions of the device missing as indicated by the break-away lines in the intermediate FOX regions.
FIG. 2B
shows the device of
FIG. 2A
after forming of a forming of a gate oxide layer, a poly gate electrode layer, a first photoresist mask PR and patterning of the gate electrode stack.
FIG. 2C
shows an N− LDD implantation into the product of
FIG. 2B
aside from peripheral areas including the FOX regions which are protected by a second photoresist mask.
FIG. 2D
shows the device of
FIG. 2C
after the heavy N+ doping ESD protection device implantation of the N+ drain/source (D/S) regions of the ESD protection devices where a third photoresist mask protects the Internal Device plus areas aside from the drain/source regions and the gate electrode stacks including the FOX regions and the entire internal device.
The additional ESD protection device implantation, as shown in
FIG. 2D
, is added into the process flow with one additional mask layer to form the NMOS without LDD peak structure. Such ESD protection device implantation is done before the formation of sidewall spacers on the gate oxide which follow as shown in FIG.
2
E.
FIG. 2E
shows the device of
FIG. 2D
after forming of sidewall spacers on the sidewalls of all of the gate electrode stacks.
FIG. 2F
shows the device of
FIG. 2E
after heavy N+ doping for the N+ D/S diffusion of the internal devices aside from the ESD protection device and peripheral areas including the FOX regions which are protected by a fourth photoresist mask.
FIG. 2G
shows the device of
FIG. 2F
after the doping of a set of P+ diffusions into P+ doped regions between the D/S regions and the FOX regions which are protected by a fifth photoresist mask.
FIG. 2H
shows the device of
FIG. 2G
after a contact hole etching step of forming contact holes CH to the P+ diffusions and the D/S regions.
The LDD peak in the ESD protection device has been covered by the implanting with an extra N+ implantation. The ESD robustness degradation due to the LDD peak in the NMOS structure can be overcome. Thus the ESD level of the ESD protection device can be improved.
Another method for improving the ESD level of the NMOS with LDD peak structure is to generate a low-breakdown-voltage junction rather than through the LDD peak structure. The process for making such an NMOS device with a lower-breakdown-voltage junction is reported in some U.S. patents [
8
-
11
].
FIG. 3
is a flow chart of a typical method of such prior art referred to herein as “Prior Art II” [
8
]. In the flowchart shown in
FIG. 3
, (Prior Art II) the method illustrated is a variation of the process of FIG.
1
. The flow starts by providing a substrate with a FOX oxide layer which is patterned as FOX regions as described above. Then form a gate-oxide and gate-poly as described above. Then perform a LDD Implantation as described above. The process is different at this stage as the next steps are to perform Cover Low-Temperature Oxide (LTO) and Form Sidewall Spacer steps. Next perform N+ Diffusion Implantation, the P+ Diffusion Implantation steps. Next perform the steps of CVD LTO and Etching of Contact Holes. Finally, the step is to perform an ESD implantation to reduce junction breakdown voltage at the end of the process. The process of
FIG. 3
is shown in detail in
FIGS. 4A-4H
which shown the typical step-by-step process flow of Prior Art II [
8
].
FIGS. 4A-4H
show the cross-sectional views of step-by-step the process flow of Prior Art II. In those cross-sectional views, the left-hand portions of the drawings show the ESD protection devices and the right-hand portions of the drawings show the internal devices.
FIG. 4A
shows a cross-sectional views of a silicon semiconductor substrate in which a P-well doped with P type dopant has been formed with FOX (field oxide) regions at each end of an ESD Protection Device on the left and an Internal device formed on the right with intermediate portions of the device missing as indicated by the break-away lines in the intermediate FOX regions.
FIG. 4B
shows the device of
FIG. 4A
after forming of a gate oxide layer, a poly gate electrode layer, a first photoresist mask and patterning of the gate electrode stack.
FIG. 4C
shows an—LDD implantation into the product of
FIG. 4B
aside from peripheral areas including the FOX regions which are protected by a second photoresist mask.
FIG. 4D
shows the device of
FIG. 4C
after forming of sidewall spacers on the sidewalls of all of the gate electrode stacks which is different

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