ESD implantation in deep-submicron CMOS technology for...

Details ESD implantation in deep-submicron CMOS technology for... ESD implantation in deep-submicron CMOS technology for...

2005-01-04

2005-01-04

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S355000

Reexamination Certificate

active

06838734

ABSTRACT:
High-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process were activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, high doping concentration ions implanted into active D/S regions formed a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. In an original drain JBV of an MOS this ESDI method is unchanged, i.e. the same as that having no such ESDI, so it can be used in I/O circuits with high-voltage signals in the deep-submicron CMOS. The ESD level of the IO ESDPD improves. The ESD discharge current path in the MOS device structure improves the ESD level in the output buffer MOS. ESDI regions are located at the output MOS devices, without covering the region under the DC. Regions under the DC without this ESDI have an unchanged JBV, so the ESDC discharges through the junction region under the DC to bulk. The original drain JBV of the output MOS with this ESDI method is unchanged, which is still the same as that having no such ESDI, to be used in the I/O circuits with high-voltage (5V) input signals in the deep-submicron CMOS with 3.3V or 2.5V VDD. This applies to diodes, FOD and lateral BJT devices.

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