Error insertion circuit for SONET forward error correction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S776000

Reexamination Certificate

active

06983414

ABSTRACT:
An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.

REFERENCES:
patent: 4597083 (1986-06-01), Stenerson
patent: 4873688 (1989-10-01), Maki et al.
patent: 5051999 (1991-09-01), Erhart et al.
patent: 5363379 (1994-11-01), Eckenrode et al.
patent: 5574717 (1996-11-01), Tomizawa et al.
patent: 5583499 (1996-12-01), Oh et al.
patent: 5642367 (1997-06-01), Kao
patent: 5673279 (1997-09-01), Oskouy et al.
patent: 5710782 (1998-01-01), Weng
patent: 5818855 (1998-10-01), Foxcroft
patent: 6199188 (2001-03-01), Shen et al.
patent: 6286123 (2001-09-01), Kim
patent: 6385751 (2002-05-01), Wolf
patent: 6571368 (2003-05-01), Chen
patent: 6683855 (2004-01-01), Bordogna et al.
patent: 6684350 (2004-01-01), Theodoras et al.
patent: 6684364 (2004-01-01), Cameron
patent: 6751743 (2004-06-01), Theodoras et al.
patent: 2002/0165962 (2002-11-01), Alvarez et al.
Christian Schuler, “Code Generation Tools For Hardware Implementation Of FEC Circuits,” GMD FOKUS, Kaiserin-Augusta-Allee 31, 10589 Berlin, Germany.
Shu Lin and Daniel J. Costello, Jr., “Error Control CodingFundamentals and Applications,” Prentice-Hall, Inc. Englewood Cliffs, New Jersey, Chapter 6, pp. 141-183.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Error insertion circuit for SONET forward error correction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error insertion circuit for SONET forward error correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error insertion circuit for SONET forward error correction will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3576030

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.