Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
Reexamination Certificate
1998-12-17
2001-09-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Transmission facility testing
Reexamination Certificate
active
06292911
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of data transfer on a high-speed data channel and, more particularly, to an error detection technique to detect errors on the channel.
2. Background of the Related Art
High-speed data channels are known in the art for use in the transfer of data between components or circuits resident on the channel. Typically, a data channel employs a particular bus architecture with data transfer protocol defined by the architecture. The channel architecture may also have certain physical requirements to ensure that the channel operates within the required design specifications. Further, the design specifications become more stringent as the rate of the data transfer increases (increase in the bandwidth) and meeting the design specification is imperative for proper operation of devices resident on the data channel.
When high-speed data channels are designed for the transfer of data between various components (such as semiconductor chips), the data channel is typically placed on a medium which also houses or supports the components. For example, to transfer data between a processor (or controller) and a separate memory not residing on-chip with the processor, a printed circuit (PC) board is utilized. The data channel is fabricated on the PC board and the components reside on the PC board. In computer parlance, this PC board is often called the “mother board” when the central processing unit (CPU) is resident thereon or a “video card” when a graphics controller is resident thereon.
One well-known high-speed data channel architecture in use is the Rambus™ data channel (or Rambus channel). The Rambus channel is a high-speed, byte-wide (9 bits), synchronous, chip-to-chip interconnect designed to achieve 600 Mega bytes per second (MB/sec) and greater data transfer rates between components on the channel. One specific Rambus channel, referred to as the Direct Rambus™ channel, is specified to transfer data at 1.6 Giga bytes per second (GB/sec) between components on the channel. In order to operate on the channel, the various components operating on the Rambus channel must interface with the channel and meet the stringent requirements imposed on these components, which are referred to as Rambus components.
In a typical layout, a number of memory components are resident on the channel along with one or more controllers or processors which manipulate the data stored in the memory. For example, the Rambus channel has strict requirements specifying the layout of the channel and the components (chips) which utilize the channel. The various chips are placed at designated locations on the board according to the design specifications. The components have the necessary interface circuitry for coupling onto the channel so that the components qualify as Rambus components. For example, dynamic random-access-memories (DRAMs) meeting the Rambus specification requirements are referred to as Rambus DRAMs or RDRAMs. The RDRAMs are capable of achieving the high speed data transfer to and from a processor (or controller) coupled onto the channel.
On any data channel, bit errors are encountered for a variety of reasons. Many of the bit errors are due to interference present when data is transferred on the channel and, on high-speed data channels, higher rates of data transfer increase the likelihood of errors due to interference. For example, when a controller chip transmits data over the channel to the memory for data storage, noise, jitter, cross-talk from other data lines, etc. can cause a given data line to have the wrong value (bit state). The cause of the error may not reside on the data path itself. Where multiple buses/links/channels are present, the cause of the interference can be from these other data paths or components coupled to them. The problem can be complicated if the error is due to a combination of these causes.
On high-speed data channels, such as the Rambus channel, error detection is difficult to achieve where a controller transmits data to the memory (store operation) and then later retrieves the data (load operation) for processing. In a simplistic approach, data can be stored in the memory, retrieved and compared with the original transmission to determine if an error occurred. However, this approach fails to determine if the error occurred during transmission or retrieval.
In another technique, signature analysis could be used to monitor the activity on the channel. However, because of the contributory interference activity of neighboring buses and components, it is difficult to determine the occurrence of an error, as well as duplicating the conditions which caused the error. Furthermore, the occurrence of the bit error may be more prevalent at a particular signal state present on the channel and such a state may be difficult to detect or even duplicate utilizing signature analysis alone. Debugging would be difficult or impossible without identifying the source(s) of the interference causing the bit error.
While bit error detection itself is not new, bit error detection has not been implemented on high-speed data channels, especially in the instance where the high-speed data channel is a subsidiary communication link separate from the main processing bus. Thus, in the personal computer (PC) environment, diagnostics associated with the central processing unit are widely utilized, but not so in high-speed data links, such as the Rambus channel. However, it is apparent that as graphics accelerators continue to increase in speed, debugging the high speed activity between the graphics accelerator and its high-speed graphics memory becomes more difficult and some form of diagnostic tool will be required for efficient debugging of the high-speed data channel.
The present invention describes a technique for introducing a scheme for detecting bit errors on the high-speed data channel, such as the Rambus channel, and further determine if a given error occurs during transmission or retrieval of data.
SUMMARY OF THE INVENTION
The present invention describes a technique for detecting an error when transferring data on a data channel between a controller and a data storage component disposed on the data channel. A test pattern is generated by the controller and transmitted on the data channel. The data storage component on the data channel receives the test pattern and tests the pattern to determine if the test pattern has been corrupted.
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Blakely & Sokoloff, Taylor & Zafman
Chase Shelly A
Cirrus Logic Inc.
De'cady Albert
Kidd William W.
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