Error correction decoder including an address generation circuit

Details Error correction decoder including an address generation circuit Error correction decoder including an address generation circuit

1997-11-17

1999-11-30

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714805, G06F 1110

Patent

active

059961074

ABSTRACT:
An error correction decoder for correcting errors in digital data includes an address generation circuit capable of generating addresses for accessing a first buffer memory and a second buffer memory. The first buffer memory preferably stores user data, and the second buffer memory stores parity code data associated with the user data. An input controller receives input data and stores the input data in the first and second buffer memories in accordance with the addresses generated by the address generation circuit. An error correction circuit receives user data and associated parity code data, performs error correction, and rewrites the corrected data and parity code data back to the respective memory areas. An output controller then read the error-corrected user data from the first buffer memory.

REFERENCES:
patent: 5239640 (1993-08-01), Froemke et al.
patent: 5844919 (1998-12-01), Glover et al.
patent: 5848076 (1998-12-01), Yoshimura

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