Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-03-13
1999-07-20
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714738, 714 30, G06F 1127
Patent
active
059251441
ABSTRACT:
An integrated circuit includes an ECC encoder having a normal mode of operation and a test mode of operation. During the test mode, the encoder is operated as a test pattern generator for computing a test pattern that exhaustively stimulates data paths, memory structures and other logic functions on the integrated circuit. A signature of responses to the test pattern can then be computed and compared to a known "correct" signature to determine whether timing faults and other types of faults exist in the integrated circuit. A disk controller chip based on such an integrated circuit can, in addition to testing its own on-chip data paths, memory structures and other logic functions, supply a test pattern to a read/write channel chip and other components on a printed circuit board assembly of a disk drive.
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Beausoliel, Jr. Robert W.
Boderman Scott T.
Shara, Esq. Milad G.
Western Digital Corporation
Young, Esq. Leo J.
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