Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-11-28
2006-11-28
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S799000
Reexamination Certificate
active
07143331
ABSTRACT:
An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The device includes a memory access circuit for controlling reading and writing of the code words to the buffer memory. Operational circuits perform a syndrome calculation with each of the multiple code words read from the buffer memory. The memory access circuit consecutively reads the multiple code words from the buffer memory and distributes the code words to the operational circuits.
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De'cady Albert
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
Trimmings John P.
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