Erase method of flash EEPROM by using snapback characteristic

Details Erase method of flash EEPROM by using snapback characteristic Erase method of flash EEPROM by using snapback characteristic

1997-10-24

2000-04-25

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular connection

36518529, 36518527, 36518533, G11C 1604

Patent

active

060551836

ABSTRACT:
A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.

REFERENCES:
patent: 5726933 (1998-03-01), Lee et al.
patent: 5828605 (1998-10-01), Peng et al.

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