Erase circuit for CMOS EEPROM

Details Erase circuit for CMOS EEPROM Erase circuit for CMOS EEPROM

1985-11-12

1988-06-14

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, 365230, G11C 700

Patent

active

047516780

ABSTRACT:
An erase circuit for an EEPROM is provided which only uses enhancement type transistors. This eliminates having to use additional processing steps to provide depletion type transistors in a CMOS process. Enhancement type transistors are used to provide the erase voltage to the control gate of an electrically erasable memory cell. An additional enhancement type transistor is used to maintain the control gate in a non-floating condition during non-erase periods.

REFERENCES:
patent: 4368524 (1983-01-01), Nakamura et al.
patent: 4599707 (1986-07-01), Fang
patent: 4616339 (1986-10-01), Cuppens et al.

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