Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-08-25
2001-12-25
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S200000
Reexamination Certificate
active
06333882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to an equilibrate and pre-charge circuit having a pulsed signal that controls connection of the equilibration circuit to an equilibration voltage.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or “data”). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as VCC/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the polarity of the voltage across the capacitor is positive or negative, represents either a logic high or a logic low value.
Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. “Access” typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one or a binary zero.
Memory devices are typically constructed with complementary digit lines of equal capacitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. Before a memory cell is selected for access, the complementary digit lines must be equilibrated. Equilibration circuits typically short the complementary digit lines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite digit lines. Conventionally, a DRAM contains one sense amplifier for a designated group (row or column) of memory cells. If the voltage level stored in the memory cell represents a binary zero, one of the digit lines will increase in level and the other digit line will decrease in level. If the voltage level stored in the selected memory cell corresponds to a binary one, a change in the opposite direction occurs. Through this complementary operation, the sense amplifier yields a single output signal which is coupled through an output buffer to an output pin of the DRAM device.
FIG. 1
illustrates a sense amplifier
30
and related circuitry of a DRAM device having a first array ARRAY0
20
and a second array ARRAY1
22
, each of which contains a plurality of memory cells
21
(illustrated in ARRAY0
20
). While only one memory cell
21
is depicted, it should be understood that each array ARRAY0
20
and ARRAY1
22
contains a plurality of such cells. A sense amplifier
30
senses the voltage level in the selected memory cell of the selected array
20
,
22
via the pair of digit lines D0
24
and D0*
26
. One of the arrays
20
,
22
is selected by the application of signals ISOa and ISOb to transistors
32
a
,
32
b
and
34
a
,
34
b
, respectively. Thus, when ISOa is driven to a logic high value and ISOb is driven to a logic low value, transistors
32
a
and
32
b
become conductive, i.e., turn on, to connect ARRAY0
20
to sense amplifier
30
while transistors
34
a
and
34
b
do not conduct, i.e., remain off, to isolate ARRAY1
22
from sense amplifier
30
. When ISOa is driven to a logic low value and ISOb is driven to a logic high value, transistors
34
a
and
34
b
turn on to connect ARRAY1
22
to sense amplifier
30
while transistors
32
a
and
32
b
remain off to isolate ARRAY0
20
from sense amplifier
30
.
Equilibration circuits
50
a
and
50
b
are provided to pre-charge the digit lines. Equilibration circuit
50
a
includes transistor
54
with a first source/drain region coupled to digit line D0
24
, a second source/drain region coupled to digit line D0*
26
and a gate coupled to receive an equilibration signal labeled EQa. Equilibration circuit
50
a
further includes transistors
56
,
58
and
60
. Transistor
56
includes a first source/drain region that is coupled to digit line D0
24
, a gate that is coupled to receive the equilibration signal EQa, and a second source/drain region that is coupled to a first source/drain region of transistor
60
. Transistor
58
includes a first source/drain region that is coupled to digit line D0*
26
, a gate that is coupled to receive the equilibration signal EQa, and a second source/drain region that is coupled to the first source/drain region of transistor
60
. Transistor
60
has a second source/drain region that is coupled to an equilibration voltage, typically Vcc/2, and a gate that is connected to a pumped Vcc voltage, Vccp, which is typically about one to two volts higher than Vcc. The application of Vccp to the gate of transistor
60
maintains transistor
60
in a constant conducting state. When the EQa signal is at a high logic level, equilibration circuit
50
a
effectively shorts digit line D0
24
to digit line D0*
26
such that both lines are equilibrated to the voltage Vcc/2. Equilibration circuit
50
b
is constructed in a similar manner to equilibration circuit
50
a
and operates when the EQb signal is at a high logic level.
When sense amplifier
30
has sensed the differential voltage across the digit lines D0
24
and D0*
26
, a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O
36
and I/O*
38
by connecting the I/O lines I/O
36
and /O*
38
to the digit lines D0
24
and D0*
26
, respectively. A column select (CSEL) signal from column select signal line
62
is applied to transistors
40
,
42
to turn them on and connect the digit lines D0
24
and D0*
26
to the I/O lines I/O
36
and I/O*
38
.
There are problems, however, with the conventional equilibration circuits
50
a
,
50
b
of
FIG. 1
, especially when a column to row short circuit, such as for example the conductor
70
between wordline
23
and digit line D0
24
illustrated in
FIG. 2
, occurs. Such short circuits may be formed during processing of the semiconductor device. During standby operation, i.e., when memory cell
21
is not being accessed, the word line WL
23
is maintained at ground and the signal EQa is high, thus turning on transistors
54
,
56
and
58
. When a short
70
does occur, a conductive path is created between ground (from wordline WL
23
) and Vcc/2 through transistors
56
and
60
. Typically, transistor
60
is sized to limit the amount of current that will pass through it when a short
70
exists. For example, the current is typically limited to approximately 40 &mgr;A. As the densities of memory circuits increase, however, the number of such row to column short circuits also increases. Thus, the total current drawn from Vcc/2 to ground by multiple shorts may be sufficient to cause a decrease in the voltage Vcc/2. A decrease in the voltage Vcc/2 will adversely affect the operation of the memory device, as the digit lines D0
24
and D0*
26
will not be properly pre-charged to the ful
Ingalls Charles L.
Merritt Todd A.
Raad George B.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Elms Richard
Micro)n Technology, Inc.
Nguyen VanTha
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