Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-03
2001-07-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000
Reexamination Certificate
active
06255164
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices and semiconductor fabrication processes, and more specifically to an electrically programmable read only memory (EPROM) cell structure and a method of forming the electrically programmable read only memory (EPROM) cell structure.
BACKGROUND OF THE INVENTION
Memory devices are one of the most important devices for storing of data and information. By storing data electrically in the memory devices, the data can be accessed with ultra high speed for various applications. The progress in memory device fabrication technology has made memories become a highly reliable and valuable device for a great amount of data reading and data writing access within an extremely short time. Various types of memories have been developed for a variety of applications like computation and communications systems.
An ideal storage device must have several characteristics. Numerous important applications of memory devices are specified with highly reliable and high speed operations. Low cost is needed for the explosively increasing demand on the more storage capability with a great number of storage units. High performance and high density are both important factors for performing reliable and high speed operations with least volume needed for the storage devices. Low power dissipation are highly demanded for providing longer operation time or greener operations especially for portable devices with limited capacity of power supply. Non-volatile or least refreshing characteristics is needed for both reliable, safety, and low power data storage.
In the category of non-volatile memories, the electrically programmable read only memory (EPROM) has become one of the important applications. An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is employed to store a bit of binary data in each cell. As a non-volatile memory, an EPROM cell can keep the status of the stored data without the need of continuing power supply for refreshing. That is, upon reapplying power, the originally-stored data is retained and the stored information can be read out without loss.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. In a conventional EPROM device, reprogramming is accomplished by first exposing the EPROM to an ultra-violet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written into the EPROM by deactivating the chip select line and switching the EPROM's data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data is connected to the data inputs and the data is written into the EPROM cell identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each cell in the EPROM array.
In an EPROM read operation, the binary data stored in the cell identified at the address inputs is connected to the chip's data output buffers. If the EPROM's chip select signal is activated, then the binary data from the selected cell is provided to the data bus.
ETOX (EPROM with Tunnel OXide) is a commonly applied cell structure for conventional EPROM devices. However, in the conventional ETOX base cell layout, there are many process limitations on the shrinking of the cell size. The limitation on accuracy and process window of present stage photo-lithography has limited the design of the ETOX cell layout. The layout design of the cell needs ertain design rules to have sufficient process window and acceptable product yield or the industrial mass fabrication.
Referring to
FIG. 1
, a schematic layout illustration of a portion of ETOX cells on integrated circuits is shown. The contact-to-polysilicon design rule A, namely the distance between a word line
2
of polysilicon and a contact
4
, is required to keep large enough for avoiding undesired short connection or leakage path under possible process shift or misalignment of patterning processes. The polysilicon-to-field-oxide design rule B, namely the distance between the word line
2
of polysilicon and the field oxide region
6
for forming common source lines (Vss lines), should be large enough for the same reason.
Therefore, under the process window limitation, the cell has to provide additional but non-functional area for the fabrication yield. The cell size of each ETOX cell on integrated circuits, which is of vital concern in making high density EPROM devices and chips, is thus increased. The cell size reduction is hard to achieve under aforementioned process concern and design rule limitation. A more dense cell layout design for making high density EPROM chips will generally tighten the process window and damage the yield and reliability of fabricated products.
SUMMARY OF THE INVENTION
The present invention propose an electrically programmable read only memory (EPROM) cell structure. Having the self-aligned approach in the provided structure and the method of forming the electrically programmable read only memory (EPROM), the conventional design rule limitation on the EPROM cell layout is eliminated.
The method for forming an electrically programmable read only memory (EPROM) cell on a semiconductor substrate mainly includes the following steps. At first, a gate insulator layer is formed on the substrate and a first conductive layer is formed on the gate insulator layer. An inter-gate dielectric layer is formed on the first conductive layer and a second conductive layer is formed on the inter-gate dielectric layer. A cap dielectric layer is formed on the second conductive layer, and the cap dielectric layer, the second conductive layer, the inter-gate dielectric layer, the first conductive layer, and the gate insulator layer are patterned to form EPROM gate structures.
Next, sidewall dielectrics are formed on the sidewalls of the EPROM gate structures, and source junctions and drain junctions are formed in the substrate under regions between the EPROM gate structures which are uncovered by the EPROM gate structures. Third conductive structures are then formed on the substrate within the sidewall dielectrics, wherein the third conductive structures respectively communicates to the source junctions and the drain junctions.
In the preferred embodiments, a series of steps can be further added for making electrical connections to the cell structure of EPROM. At first, an inter-layer dielectric layer is formed over the substrate covering the EPROM gate structures and the third conductive structures. A portion of the inter-layer dielectric layer is removed to define contact openings to a portion of the third conductive structures, and an interconnection layer is formed on the inter-layer dielectric and within the contact openings in order to electrically couple with the portion of the third conductive structures.
The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line.
The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region. The self-aligned drain contact neighbors the first dielectric layer, and is above the substrate on a portion of the drain junction region. The second dielectric layer c
Liu Chia-Chen
Wang Ling-Sung
Booth Richard
Worldwide Semiconductor Manufacturing Corp.
LandOfFree
EPROM cell structure and a method for forming the EPROM cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with EPROM cell structure and a method for forming the EPROM cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EPROM cell structure and a method for forming the EPROM cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2567870