Epitaxially grown fin for FinFET

Details Epitaxially grown fin for FinFET Epitaxially grown fin for FinFET

2003-08-05

2004-12-28

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S192000

Reexamination Certificate

active

06835618

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).
BACKGROUND ART
Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk metal oxide semiconductor field effect transistor (MOSFET) devices below the 0.1 &mgr;m process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.
Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. A FinFET is a recent double-gate structure that includes a channel formed in a vertical fin. The FinFET is similar to existing planar MOSFETs in layout and fabrication. The FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.
Fins of existing FinFETs are conventionally formed by direct etching of the layer of material that is to form the fin channel. This conventional direct etching can lead to rough fin sidewalls and, possibly, damage to the fin sidewalls. Such roughness and/or damage can negatively impact the performance of the eventual constructed FinFET. Therefore, there exists a need for methods for forming a fin of a FinFET that avoids the use of direct etching.
DISCLOSURE OF THE INVENTION
Consistent with the present invention, a method of growing a fin of a FinFET transistor is provided that avoids the use of direct etching. An epitaxial growth process may be employed for growing a fin within a trench of a layer of material, such as, for example, an oxide layer. By growing the fin, instead of using an etching process, the resulting fin will have a relatively damage free surface, thereby improving FinFET performance.
Additional advantages and other features of the invention will be set forth in part in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a FinFET. The FinFET includes a substrate and a fin channel epitaxially grown on the substrate. The FinFET further includes source and drain regions formed adjacent the fin channel.
According to another aspect of the invention, a structure for constructing a FinFET transistor is provided. The structure includes a seed layer and a layer of a first material formed on the seed layer, the layer of first material having a trench. The structure further includes a fin epitaxially grown in the trench.
According to a further aspect of the invention, a method of forming a fin for a FinFET is provided. The method includes defining a trench in a layer of first material and growing a second material in the trench to form the fin. The method further includes removing the layer of first material.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 2003/0197194 (2003-10-01), Fried et al.
patent: 2004/0075122 (2004-04-01), Lin et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.

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