Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state
Reexamination Certificate
2011-04-12
2011-04-12
Kunemund, Robert M (Department: 1714)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
C117S090000, C117S095000
Reexamination Certificate
active
07922813
ABSTRACT:
Epitaxially coated silicon wafers, are produced by epitaxially coating a multiplicity of wafers polished at least on their front sides, successively and individually in an epitaxy reactor, by placing a silicon wafer on a susceptor, pretreating under a hydrogen atmosphere followed by addition of an etching medium to the hydrogen atmosphere, coating epitaxially on the polished front side and removing the water from the epitaxy reactor. The susceptor is then heated, in each case, to a temperature of at least 1000° C. under a hydrogen atmosphere, and furthermore an etching treatment of the susceptor and a momentary coating of the susceptor with silicon are effected after a specific number of epitaxial coatings. Silicon wafers characterized by a parameter R30-1 mm of −10 nm to +10 nm, determined at a distance of 1 mm from the edge of the silicon wafer are produced.
REFERENCES:
patent: 4057939 (1977-11-01), Basi
patent: 5400548 (1995-03-01), Huber et al.
patent: 5532183 (1996-07-01), Sugawara
patent: 6277715 (2001-08-01), Takeno et al.
patent: 6478883 (2002-11-01), Tamatsuka et al.
patent: 6630024 (2003-10-01), Schmolke et al.
patent: 6899762 (2005-05-01), Wenski et al.
patent: 6995077 (2006-02-01), Siebert et al.
patent: 2001/0032581 (2001-10-01), Wilson et al.
patent: 2001/0039917 (2001-11-01), Arai et al.
patent: 2003/0068502 (2003-04-01), Togashi et al.
patent: 2003/0104222 (2003-06-01), Ono et al.
patent: 2003/0175532 (2003-09-01), Asayama et al.
patent: 2004/0005777 (2004-01-01), Qu et al.
patent: 2004/0065250 (2004-04-01), Komiya et al.
patent: 2004/0089225 (2004-05-01), Ono et al.
patent: 2004/0115941 (2004-06-01), Siebert et al.
patent: 2004/0241992 (2004-12-01), Kono et al.
patent: 2005/0087830 (2005-04-01), Takeno
patent: 2005/0160971 (2005-07-01), Otsuka
patent: 2006/0201413 (2006-09-01), Nishizawa
patent: 2007/0066036 (2007-03-01), Schauer et al.
patent: 2008/0118712 (2008-05-01), Schauer et al.
patent: 198 33 257 (1999-09-01), None
patent: 199 38 340 (2001-02-01), None
patent: 100 25 871 (2001-12-01), None
patent: 0 272 531 (1988-06-01), None
patent: 0 547 894 (1993-06-01), None
patent: 0 580 162 (1994-01-01), None
patent: 1209251 (2002-05-01), None
patent: 2001508599 (2001-06-01), None
patent: 2003 163216 (2003-06-01), None
patent: 2003 309707 (2003-10-01), None
patent: 2003 318109 (2003-11-01), None
patent: 2004 175658 (2004-06-01), None
patent: 165489 (2004-06-01), None
patent: 2004-243505 (2004-09-01), None
patent: 2004253751 (2004-09-01), None
patent: 2004 335528 (2004-11-01), None
patent: 2004 356416 (2004-12-01), None
patent: 2005 011880 (2005-01-01), None
patent: 2005 39111 (2005-02-01), None
patent: 2005 197278 (2005-07-01), None
patent: 1227286 (1988-08-01), None
patent: 1228549 (2005-03-01), None
patent: 9832893 (1998-07-01), None
patent: WO 03/044845 (2003-05-01), None
patent: WO 2005/001916 (2005-01-01), None
Doubleside polishing-a technologymandatoryfor 300mm wafer manufacturing G. Wenski*, T. Altmann, W. Winkler, G. Heier, G. H.olker Department B-LW-TP, Wacker Siltronic AG, P.O. Box 1140, D-84479 Burghausen, Germany Materials Science in Semiconductor Processing 5 (2003) 375-380, pp. 375-380.
Mike Seacrist, SCP Symposium—Jun. 2005—Seacrist Silicon Starting Materials for Sub-65nm Technology Nodes MEMC Electronic Materials, St. Peters MO, 63376 pp. 1-10.
Wafer-Edge Challenges SEMI STEP Wafer Edge Profile SEMICON/West 2006 Tetsuo Fukuda SEMI Japan (Fujitsu) Japan Advanced Wafer Geometry Task Force Semi Japan pp. 1-21 PwrPt Presentation.
English Abstract corresponding to JP 2003309707 A.
English Abstract corresponding to JP 2003318109 A.
English Abstract corresponding to JP 2003163216 A.
English Abstract corresponding to JP 2004335528 A.
English Abstract corresponding to JP 2004356416 A.
English Abstract corresponding to JP 2005039111 A.
English Abstract corresponding to JP 2005197278 A.
English Abstract corresponding to JP 2005011880 A.
English Abstract corresponding to JP 2004165489 A.
English Abstract corresponding to WO 03/044845 A1.
U.S. Publication No. 2004/0089225A1 is the English equivalent to JP 2004175658 A.
U.S. Patent No. 6,478,883 B1 is the English equivalent to TW 1227286.
U.S. Publication No. 2001/0032581 A1 is the English equivalent to TW 1228549.
English Derwent Abstract AN 1999-519699 corresponding to DE 198 33 257C1.
Japanese Journal of Applied Physics, vol. 38, (1999), pp. 38-39.
Tsutomu et al. “Precise Measurement of Wafer Geometry Using Interferometric Methods”, Kobe Steel Engineering Reports, Japan, vol. 55, No. 1, Apr. 2005, p. 45-47.
Hager Christian
Schauer Reinhard
Brooks & Kushman P.C.
Kunemund Robert M
Siltronic AG
LandOfFree
Epitaxially coated silicon wafer and method for producing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Epitaxially coated silicon wafer and method for producing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Epitaxially coated silicon wafer and method for producing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2656606