Epitaxially coated semiconductor wafer and process for...

Details Epitaxially coated semiconductor wafer and process for... Epitaxially coated semiconductor wafer and process for...

2005-05-31

2005-05-31

Hiteshew, Felisa (Department: 1765)

Single-crystal, oriented-crystal, and epitaxy growth processes;

Forming from vapor or gaseous state

With decomposition of a precursor

C117S092000, C117S094000

Reexamination Certificate

active

06899762

ABSTRACT:
A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRmaxof less than or equal to 0.13 μm and a maximum density of 0.14 scattered light centers per cm2. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 μm×1 μm reference area. Furthermore, there is a process for producing the semiconductor wafer. The process includes the following process steps: (a) as a single polishing step, simultaneous polishing of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while an alkaline polishing slurry is being supplied, the semiconductor wafer lying in a cutout of a carrier whose thickness is dimensioned to be 2 to 20 μm less than the thickness of the semiconductor wafer after the latter has been polished; (b) simultaneous treatment of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while a liquid containing at least one polyhydric alcohol having 2 to 6 carbon atoms is being supplied; (c) cleaning and drying of the semiconductor wafer; and (d) deposition of the epitaxial layer on the front surface of the semiconductor wafer produced in accordance with steps (a) to (c).

REFERENCES:
patent: 3691694 (1972-09-01), Goetz et al.
patent: 6030887 (2000-02-01), Desai et al.
patent: 198 33 257 (1999-09-01), None
patent: 0 208 315 (1990-09-01), None
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patent: 0 711 854 (1996-05-01), None
patent: 0 887 152 (1998-12-01), None
1997 National Technology Roadmap for Semi-conductors (NTRS), Semiconductor Industry Association (SIA), San Jose, Table 20, p. 64-66.
English Derwent Abstract AN 1999-519699 [44] corresp. to DE 198 33 257.
English Derwent Abstract AN 1987-008979 [02] corresp. to EP 0 208 315.
English application text corresp. to 199 05 737.0.

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