Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth
Reexamination Certificate
2001-06-05
2003-05-20
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth from liquid or supercritical state
Having pulling during growth
C117S003000, C117S020000, C117S035000, C117S932000, C148S033100, C148S033300
Reexamination Certificate
active
06565649
ABSTRACT:
BACKGROUND OF THE INVENTION
The process of the present invention relates generally to the preparation of epitaxial silicon wafers. More particularly, the present invention relates to the preparation of a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier, each wafer having an epitaxial layer which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on a surface of a substrate upon which the epitaxial layer is grown.
Single crystal silicon, from which a single crystal silicon wafer may be obtained, is commonly prepared by the so-called Czochralski (“Cz”) method. In this method, polycrystalline silicon (“polysilicon”) is charged to a crucible and melted, a seed crystal is brought into contact with the molten silicon and a single crystal is grown by slow extraction. After formation of a neck is complete, the diameter of the crystal is enlarged by decreasing the pulling rate and/or the melt temperature until the desired or target diameter is reached. The cylindrical main body of the crystal which has an approximately constant diameter is then grown by controlling the pull rate and the melt temperature while compensating for the decreasing melt level. Near the end of the growth process but before the crucible is emptied of molten silicon, the crystal diameter must be reduced gradually to form an end-cone. Typically, the end-cone is formed by increasing the crystal pull rate and heat supplied to the crucible. When the diameter becomes small enough, the crystal is then separated from the melt.
In recent years, it has been recognized that a number of defects in single crystal silicon form in the crystal growth chamber as the crystal cools after solidification. Such defects arise, in part, due to the presence of an excess (i.e., a concentration above the solubility limit) of intrinsic point defects, which are known as vacancies and self-interstitials. Silicon crystals grown from a melt are typically grown with an excess of one or the other type of intrinsic point defect, either crystal lattice vacancies (“V”) or silicon self-interstitials (“I”). It has been suggested that the type and initial concentration of these point defects in the silicon are determined at the time of solidification and, if these concentrations reach a level of critical supersaturation in the system and the mobility of the point defects is sufficiently high, a reaction, or an agglomeration event, will likely occur. Agglomerated intrinsic point defects in silicon can severely impact the yield potential of the material in the production of complex and highly integrated circuits.
Vacancy-type defects are recognized to be the origin of such observable crystal defects as D-defects, Flow Pattern Defects (FPDs), Gate Oxide Integrity (GOI) Defects, Crystal Originated Particle (COP) Defects, crystal originated Light Point Defects (LPDs), as well as certain classes of bulk defects observed by infrared light scattering techniques such as Scanning Infrared Microscopy and Laser Scanning Tomography. Also present in regions of excess vacancies are defects which act as the nuclei for ring oxidation induced stacking faults (OISF). It is speculated that this particular defect is a high temperature nucleated oxygen agglomerate catalyzed by the presence of excess vacancies.
Defects relating to self-interstitials are less well studied. They are generally regarded as being low densities of interstitial-type dislocation loops or networks. Such defects are not responsible for gate oxide integrity failures, an important wafer performance criterion, but they are widely recognized to be the cause of other types of device failures usually associated with current leakage problems.
Epitaxial silicon growth typically involves a chemical vapor deposition process wherein a substrate, such as a single crystal silicon wafer, is heated while a gaseous silicon compound is passed over the wafer surface to affect pyrolysis or decomposition. When a single crystal silicon wafer is used as the substrate, the silicon is deposited in such a way as to continue the growth of the single crystal structure. As a result, defects present on the substrate surface, such as agglomerated silicon self-interstitial defects, may directly impact the quality of the resulting epitaxial wafer. This impact on quality is due to the fact that, by continuing the growth of the single crystal structure, defects present on the substrate surface may continue growth, resulting in the formation of new crystal defects, i.e., grown-in defects, in the epitaxial layer. For example, epitaxial defects such as mounds, epitaxial stacking faults and hillocks, having a maximum cross-sectional width ranging from the current detection limit of a laser-based auto-inspection device of about 0.1 microns to greater than about 10 microns, can be formed.
To date, the primary approach to the grown-in defect problem has been to inspect the surface of the substrate prior to epitaxial deposition. However, such an approach is time consuming; it is also not always successfully in identifying and eliminating problem substrates prior to the deposition process. Accordingly, a need continues to exist for a process whereby substrates are reliably and consistently provided for epitaxial deposition which have surfaces that are substantially free of agglomerated interstitial defects, and thus eliminate the grown-in defects associated therewith.
SUMMARY OF THE INVENTION
Among the objects of the present invention, therefore, is the provision of a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier, each wafer having an epitaxial layer which is substantially free of grown-in defects; the provision of such an epitaxial wafer having a single crystal silicon substrate with an axially symmetric region which is substantially free of agglomerated silicon self-interstitial defects; the provision of such a substrate which may additionally have an axially symmetric region of vacancy dominated material which is substantially free of agglomerated vacancy defects.
Briefly, therefore, the present invention is directed to a set of epitaxial silicon wafers, each epitaxial wafer comprising a single crystal silicon substrate having an epitaxial silicon layer deposited thereon. The substrate has a central axis, a front surface and a back surface which are generally perpendicular to the central axis, a circumferential edge, and a radius extending from the central axis to the circumferential edge. The substrate comprises an axially symmetric region of silicon self-interstitial dominated material which is substantially free of agglomerated interstitial defects, the axially symmetric region extending radially inwardly from the circumferential edge of the substrate. The epitaxial layer deposited upon a surface of the substrate is substantially free of grown-in defects caused by the presence of agglomerated interstitial defects on the surface of the substrate. other objects will be in part apparent and in part pointed out hereinafter.
REFERENCES:
patent: 4314595 (1982-02-01), Yamamoto et al.
patent: 4981549 (1991-01-01), Yamashita et al.
patent: 5264189 (1993-11-01), Yamashita et al.
patent: 5474020 (1995-12-01), Bell et al.
patent: 5485803 (1996-01-01), Habu
patent: 5487354 (1996-01-01), von Ammon et al.
patent: 5502010 (1996-03-01), Nadahara et al.
patent: 5593494 (1997-01-01), Falster
patent: 5667584 (1997-09-01), Takano et al.
patent: 5704973 (1998-01-01), Sakurada et al.
patent: 5728211 (1998-03-01), Takano et al.
patent: 5789309 (1998-08-01), Hellwig
patent: 5846322 (1998-12-01), Schulmann et al.
patent: 5919302 (1999-07-01), Falster et al.
patent: 5935320 (1999-08-01), Graef et al.
patent: 5942032 (1999-08-01), Kim et al.
patent: 5954873 (1999-09-01), Hourai et al.
patent: 5968262 (1999-10-01), Saishouji et al.
patent: 5968264 (1999-10-01), Iida et al.
patent: 6045610 (2000-04-01), Park et al.
patent: 6053974 (2000-04-01), Luter et al.
patent: 6093913 (2000-07-01), Schrenker et al.
patent: 615
Falster Robert J.
Fei Lu
Holzer Joseph C.
Korb Harold W.
Mule′Stagno Luciano
Kunemund Robert
MEMC Electronic Materials , Inc.
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