Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-06-22
2002-07-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S291000
Reexamination Certificate
active
06426279
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and manufacturing process, and more particularly to methods for forming retrograde channel profiles within a semiconductor devices.
BACKGROUND ART
The principal elements of a typical metal-oxide-semiconductor (MOS) device generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped polysilicon semiconductor. Heavily doped source/drain regions are formed in the semiconductor substrate and are connected to source/drain terminals. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The gate electrode is generally separated from the semiconductor substrate by an insulating layer to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electrical field is set up in the channel region. By varying the transverse electric field between the source and drain regions, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner, an electric field controls the current flow through the channel region. The channel is typically lightly doped with an impurity type opposite to that of the source/drain regions, and the impurity concentration profile is typically uniform from the surface toward the direction of depth, as shown by line a in FIG.
3
.
In particular MOSFET devices, a channel implantation process is frequently performed to augment the substrate doping of the same conductivity. Thus, for an NMOS device, a p-type impurity is ion implanted into the substrate and channel region, and for a PMOS device, an n-type impurity is ion implanted into the substrate and channel region. The purposes of this channel implantation are typically to adjust threshold voltages and improve short channel characteristics, and many approaches have been introduced, such as a retrograde well structure for that purposes. As shown by curve b in
FIG. 3
, the retrograde well structure generally has an impurity concentration peak deep under the surface. A method for manufacturing a retrograde well structure in semiconductor devices is disclosed in U.S. Pat. No. 5,726,488 by Watanabe, et al. According to Watanabe, et al., a retrograde well structure is achieved by forming an epitaxial layer on a semiconductor substrate having a highly doped boron layer, formed by ion implantation, in its surface. As shown in
FIG. 1A
, a lightly doped P type silicon substrate
10
is prepared and the first oxide film
12
is formed thereon. A first photoresist layer
14
is formed on the first oxide film
12
. In
FIG. 1B
, after patterning the first photoresist layer
14
to expose a portion of the top surface of the first oxide film
12
, boron is ion implanted, as shown by arrows A, into the first oxide film
12
at an implantation dosage of between 5×10
12
atoms cm
−2
to 2×10
13
atoms cm
−2
and at an implantation energy of 50 KeV, thereby forming a high concentration layer
16
in the surface of the substrate
10
. As shown in
FIG. 1C
, after removing the first photoresist layer
14
and the first oxide film
12
, an epitaxial layer
18
is formed on the substrate
10
including the high concentration layer
16
at a thickness of between 0.8 &mgr;m to 1.7 &mgr;m. Then, as shown in
FIG. 1D
, a second oxide film
20
is formed on the epitaxial layer
18
, and a nitride film
22
is formed on the second oxide film
22
. A second photoresist layer
24
is formed on the nitride film
22
. As shown in
FIG. 1E
, after patterning the second photoresist layer
24
and the nitride film
22
to expose a portion of the surface of the epitaxial layer
18
overlying the high concentration layer
16
, BF
2
ions are implanted, as shown by arrows B, into the second oxide film
20
at an implantation dosage of 2×10
12
atoms cm
−2
and an implantation energy of 60 KeV, thereby forming a low impurity region
26
within the epitaxial layer
18
. As shown in
FIG. 1F
, after removing the second oxide film
20
, the nitride film
22
, and the second photoresist layer
24
from the top surface of the epitaxial layer
18
, an annealing process is performed to repair the lattice damage by the previous ion implantation. A gate oxide layer
28
is then formed on the low impurity region
26
, and local isolation regions
29
are formed on the epitaxial layer
18
. In
FIG. 1G
, a gate electrode
30
is formed on the gate oxide
28
with sidewall spacers
32
. Then, n-type active regions
34
are formed by ion implanting arsenic ions at an implantation dosage of 3×10
16
cm
−2
and at an implantation energy of 80 KeV.
Although the method disclosed in Watanabe et al. provides a relatively simple method to form a retrograde channel profile, the implanted boron atoms contained in the high concentration layer
16
are easily diffused into the overlying epitaxial layer
18
by the subsequent fabrication steps e.g., annealing, thereby degrading the carrier mobility of the channel region and the channel inversion charge density.
Thus, there is a continuing need for improved methods that form a super-steep retrograde impurity profile to improve the channel carrier mobility and the channel inversion charge density, thereby improving devices' speed performance.
SUMMARY OF THE INVENTION
An advantage of the present invention is an efficient and production-worthy method of manufacturing a semiconductor device having a retrograde channel profile to improve devices' speed performance.
Another advantage of the present invention is a simplified and improved method of manufacturing a super steep retrograde channel profile.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises: forming a high impurity concentration layer of a first conductive type on a main surface of a semiconductor substrate; introducing a non-dopant into the high concentration impurity layer to form a diffusion cap layer near a top surface of the high concentration impurity layer; and forming a low impurity concentration layer of the first conductive type on the surface of the first semiconductor layer. The diffusion cap layer formed between the high impurity concentration layer and the low impurity concentration layer substantially prevents impurity atoms contained in the high concentration layer from diffusing into the low impurity concentration layer.
Another aspect of the present invention is a semiconductor device comprising: a silicon substrate having a main surface; a high impurity concentration layer of a first conductive type formed on the main surface of the silicon substrate, the high impurity concentration layer comprising a diffusion cap layer formed near a top surface of the high impurity concentration layer; and a low impurity concentration layer of the first conductive type formed on the top surface of the high impurity concentration layer.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of o
Huster Carl
Ishida Emi
Advanced Micro Devices , Inc.
Lattin Christopher
Niebling John F.
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