Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-30
2000-09-05
Pham, Long
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438268, 438269, 438259, 438589, H01L 21336
Patent
active
061142050
ABSTRACT:
A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench hat extends vertically through those regions. A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain A region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.
REFERENCES:
patent: 3924265 (1975-12-01), Rodgers
patent: 3975221 (1976-08-01), Rodgers
patent: 4003036 (1977-01-01), Jenne
patent: 4987090 (1991-01-01), Hsu et al.
patent: 4992838 (1991-02-01), Mori
patent: 5016067 (1991-05-01), Mori
patent: 5016068 (1991-05-01), Mori
patent: 5071782 (1991-12-01), Mori
patent: 5078498 (1992-01-01), Kadakia et al.
patent: 5124764 (1992-06-01), Mori
patent: 5141886 (1992-08-01), Mori
patent: 5160491 (1992-11-01), Mori
patent: 5621234 (1997-04-01), Kato
patent: 5770514 (1998-06-01), Matsuda et al.
patent: 5879971 (1999-03-01), Witek
patent: 5893742 (1999-04-01), Demirlioglu et al.
Solid State Electronic Devices, Third Edition, 1990 (month unknown); 325-327 and 347-350; Ben G. Streetman; Prentice Hall; Englewood Cliffs, New Jersey 07632.
T. J. Rodgers, and J. D. Meindl, "VMOS: High-Speed TTL Compatible MOS Logic." IEEE Journal of Solid-State Circuits, vol. SC-9, No. 5, Oct. 1974, pp. 239-250.
K. Mori, "Sub-half Micron Device Fabricated with Two Microns Generation Facilities." The Proceedings of the 1998 SPIE International Conference on Microelectronics Device Technology, pp. 132-140.
J. Nishizawa, N. Takeda, and S. Suzuki, "U-Grooved SIT CMOS Technology with 3 fJ and 49 ps (7 mW, 350 fJ) Operation." IEEE Transactions on Electron Devices, vol. 37, No. 8, Aug. 1990, pp. 1877-1883.
L. Risch, W. Krautschneider, and F. Hofmann, "Vertical MOS Transistor with 70 nm Channel Length." IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp 1495-1498.
V. Dudek, W. Appel, and L. Beer, "Lithography-Independent Nanometer Silicon MOSFET's on Insulator." IEEE Transactions on Electron Devices, vol. 43, No. 10, Oct. 1996, pp 1626-1631.
W. F. Richardson, D.M. Bordelon, and G. P. Pollack, "A Trench Transistor Cross-Point Dram Cell." The Proceedings of IEEE International Electron Device Meeting, Dec. 1985, pp. 714-717.
G. Rittenhouse, W. Mansfield, and A. Kornblit, "Sub-0.1 .mu.m NMOS Transistor Fabricated Using Laser Plasma Point-Source X-Ray Lithography." IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995, pp. 322-324.
S. Maeda, T. Ipposhi, and H. Nishimura, "Impact of a Vertical O-Shape Transistor Cell for 1 Gbit DRAM and Beyond." IEEE Transactions on Electron Devices, vol. 42, No. 12, Dec. 1995, pp. 2117-2123.
M. Cao, T. Kamins, and P. Voorde, "0.18-.mu.m Fully-Depleted Silicon-on-Insulator MOSFET's." IEEE Electron Device Letters, vol. 18, No. 6, Jun. 1997, pp. 251-253.
S. Nakajima, K. Miura, and T. Somatani, "A Trench MOSFET with Surface Source/Drain Contacts." The Proceedings of IEEE International Electron Device Meeting, Dec. 1985, pp. 200-203.
Pham Long
Sony Corporation
Sony Electronics Inc.
Tobin Christopher M.
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