Enhancing strained device performance by use of multi narrow...

Details Enhancing strained device performance by use of multi narrow... Enhancing strained device performance by use of multi narrow...

2006-09-05

2006-09-05

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S938000

Reexamination Certificate

active

07101765

ABSTRACT:
A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

REFERENCES:
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6607948 (2003-08-01), Sugiyama et al.
patent: 6627506 (2003-09-01), Kuhn et al.
patent: 6657223 (2003-12-01), Wang et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 2004/0212035 (2004-10-01), Yeo et al.
patent: 2005/0032275 (2005-02-01), Akio et al.
patent: WO 03/050871 (2003-06-01), None
Shimizu A, et al.: “Local Mechanical-Stress Control (LMC):A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting2001.IEDM. Technical Digest. Washington D.C., Dec. 2-5, 2001, pp. 433-436.
Ito. S, et al. “Effect of Mechanical Stress Induced by Etch-Stop Nitride: Impact on Deep Submicron Transistor Performance”, Microelectronics Reliability Elsevier U.K, vol. 42, No. 2, Feb. 2002, pp. 201-209.
PCT International Search Report for PCT Application No. PCT/US2005/010159. Mailed Jun. 30, 2005, (7 pages).
Rim, Kern, et al., “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's,” IEEE Transaction on Electron Devices, vol. 47, No. 7, Jul. 2000, pp. 1406-1415.

Affiliated with

Also associated with

Rating

Enhancing strained device performance by use of multi narrow... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhancing strained device performance by use of multi narrow..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhancing strained device performance by use of multi narrow... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3547101